A microprocessor according to the present invention comprises a sub-read bus (203), to which output terminals of registers (6) of a register file of the microprocessor are coupled. The sub-read bus is in turn coupled to a main read bus (201) of the microprocessor through a bus output circuit (18). Upon occurrence of a read access to any of the registers (16), the bus output circuit (18) couples the sub-read bus (203) with the main read bus (201), whereby data read out from the registers (16) to the sub-read bus are transmitted to the main read bus (201), and under no existence of the read access, the bus output circuit interrupts the data transmission from the sub-read bus to the main read bus. With this, a load capacitance of the read bus is reduced. As a result, an access time for access to the read bus is reduced.