An array processor wherein data coming out of an internal data memory device (22) is fed into a register file (24), and on the same clock cycle, three data results are coming out of an arithmetic unit (26, 28, 30) and feed back into the register file. Therefore, on a single clock cycle, five separate pieces of data are going into the register file. In the same clock cycle, other data coming out of the outputs of the register file (24) feed data into two separate floating arithmetic adders (26, 28) and one floating arithmetic multiplier (30). The arrangement allows a constant flow of data to be supplied to the arithmetic unit thereby using the arithmetic unit to its maximum functioning ability.