The circuit arrangement comprises, for each bit location in a column of the RAM, an input shift register, a multiplexer and a comparator. The input data bit is stored in the shift register, and the multiplexer is arranged during a write cycle, to write the data bit into the bit position. During a verification cycle, the multiplexer is arranged to write the inverse data bit into the same position, and the comparator compares the output bit position of the RAM with the inverse data bit The result is stored in the shift register, which can be down-loaded for analysis.