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公开(公告)号：EP0573152B1
公开(公告)日：1997-01-15
申请号：EP93303647.7
申请日：1993-05-11
发明人： Hastie, Neil Stuart
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17704
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2.发明公开Circuit arrangement for verifying data stored in a random access memory 失效希特勒诺·恩·祖尔·普鲁芬在“einem Direktzugriffsspeicher gespeicherten Daten”中。
公开(公告)号：EP0382453A2
公开(公告)日：1990-08-16
申请号：EP90301184.9
申请日：1990-02-05
CPC分类号： G06F11/0751 , G06F11/267 , G11C29/30 , G11C29/36
摘要： The circuit arrangement comprises, for each bit location in a column of the RAM, an input shift register, a multiplexer and a comparator. The input data bit is stored in the shift register, and the multiplexer is arranged during a write cycle, to write the data bit into the bit position. During a verification cycle, the multiplexer is arranged to write the inverse data bit into the same position, and the comparator compares the output bit position of the RAM with the inverse data bit The result is stored in the shift register, which can be down-loaded for analysis.
摘要翻译： 对于RAM的列中的每个比特位置，电路装置包括输入移位寄存器，多路复用器和比较器。 输入数据位存储在移位寄存器中，多路复用器在写周期期间被布置，以将数据位写入位位置。 在验证周期期间，多路复用器被布置为将逆数据位写入相同位置，并且比较器将RAM的输出位位置与逆数据位进行比较结果存储在移位寄存器中， 加载分析。
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3.发明授权Circuit arrangement for verifying data stored in a random access memory 失效用于将存储在随机存取存储器中的数据的检测数据的电路装置
公开(公告)号：EP0382453B1
公开(公告)日：1996-06-19
申请号：EP90301184.9
申请日：1990-02-05
CPC分类号： G06F11/0751 , G06F11/267 , G11C29/30 , G11C29/36
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公开(公告)号：EP0573175A3
公开(公告)日：1994-04-06
申请号：EP93303844.0
申请日：1993-05-18
IPC分类号： H03K19/173
CPC分类号： H03K19/1737
摘要： A programmable logic cell (7) has two inputs (a,b) and six outputs (1-6), each output being a different logical function of the inputs. Each output (1-6) is generated by a pair of NMOS transistors, one transistor of each pair having its gate connected to one of the inputs (a) and the other transistor of each pair having its gate connected to the inverse (b) of the same input.
摘要翻译： 可编程逻辑单元（7）具有两个输入（a，b）和六个输出（1-6），每个输出是输入的不同逻辑功能。 每个输出（1-6）由一对NMOS晶体管产生，每对中的一个晶体管的栅极连接到输入端（a）中的一个，而每对中的另一个晶体管的栅极连接到反相器（b） 相同的投入。
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公开(公告)号：EP0573175A2
公开(公告)日：1993-12-08
申请号：EP93303844.0
申请日：1993-05-18
IPC分类号： H03K19/173
CPC分类号： H03K19/1737
摘要： A programmable logic cell (7) has two inputs (a,b) and six outputs (1-6), each output being a different logical function of the inputs. Each output (1-6) is generated by a pair of NMOS transistors, one transistor of each pair having its gate connected to one of the inputs (a) and the other transistor of each pair having its gate connected to the inverse (b) of the same input.
摘要翻译： 可编程逻辑单元具有两个输入和六个输出，每个输出是输入的不同逻辑功能。 每个输出由一对NMOS晶体管产生，每对NMOS晶体管的一个晶体管的栅极连接到一个输入，另一个晶体管的栅极连接到同一输入的反相。
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公开(公告)号：EP0573152A3
公开(公告)日：1994-04-06
申请号：EP93303647.7
申请日：1993-05-11
发明人： Hastie, Neil Stuart
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17704
摘要： A programmable logic cell suitable for use in a programmable gate array and able to produce any logical function of two inputs, operate as a 2 to 1 multiplexor or a data latch is formed by four multiplexors (1,2,3,4), five inverters (12,13,15,16,17) and an OR gate (14) to provide a very fast programmable logic cell.
摘要翻译： 可编程逻辑单元适用于可编程门阵列并能产生两个输入的任何逻辑功能，作为2至1多路复用器或数据锁存器由四个多路复用器（1,2,3,4），五个 反相器（12,13,15,16,17）和一个或门（14），以提供一个非常快速的可编程逻辑单元。
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公开(公告)号：EP0573152A2
公开(公告)日：1993-12-08
申请号：EP93303647.7
申请日：1993-05-11
发明人： Hastie, Neil Stuart
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17704
摘要： A programmable logic cell suitable for use in a programmable gate array and able to produce any logical function of two inputs, operate as a 2 to 1 multiplexor or a data latch is formed by four multiplexors (1,2,3,4), five inverters (12,13,15,16,17) and an OR gate (14) to provide a very fast programmable logic cell.
摘要翻译： 可编程逻辑单元适用于可编程门阵列并且能够产生两个输入的任何逻辑功能，作为2至1多路复用器或数据锁存器由四个多路复用器，五个反相器和“或”门形成，以提供非常 快速可编程逻辑单元。
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8.发明公开
公开(公告)号：EP0382453A3
公开(公告)日：1991-10-02
申请号：EP90301184.9
申请日：1990-02-05
CPC分类号： G06F11/0751 , G06F11/267 , G11C29/30 , G11C29/36
摘要： The circuit arrangement comprises, for each bit location in a column of the RAM, an input shift register, a multiplexer and a comparator. The input data bit is stored in the shift register, and the multiplexer is arranged during a write cycle, to write the data bit into the bit position. During a verification cycle, the multiplexer is arranged to write the inverse data bit into the same position, and the comparator compares the output bit position of the RAM with the inverse data bit The result is stored in the shift register, which can be down-loaded for analysis.
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