发明公开
- 专利标题: APPARATUS FOR MULTIPLICATION, DIVISION AND EXTRACTION OF SQUARE ROOT
- 专利标题(中): 装置,方法和方法提取方法
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申请号: EP89912134申请日: 1989-11-02
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公开(公告)号: EP0394499A4公开(公告)日: 1993-02-24
- 发明人: NARITA, MASAHISA , KAZIWARA, HISASHI , ASAI, TAKESHI , MORINAGA, SHIGEKI , KIDA, HIROYUKI , WATABE, MITSURU , NAKAMIKAWA, TETSUAKI , KAWASAKI, SHUNPEI , TATEZAKI, JUNICHI , NAKAGAWA, NORIO , KASHIWAGI, YUGO
- 申请人: HITACHI, LTD. , HITACHI ENGINEERING CO., LTD.
- 申请人地址: 6, KANDA SURUGADAI 4-CHOME; CHIYODA-KU, TOKYO 100
- 专利权人: HITACHI, LTD.,HITACHI ENGINEERING CO., LTD.
- 当前专利权人: HITACHI, LTD.,HITACHI ENGINEERING CO., LTD.
- 当前专利权人地址: 6, KANDA SURUGADAI 4-CHOME; CHIYODA-KU, TOKYO 100
- 优先权: JP30996888 1988-12-09; JP29024888 1988-11-18; JP27724288 1988-11-04
- 主分类号: G06F7/52
- IPC分类号: G06F7/52 ; G06F7/552 ; G06F7/57
摘要:
An apparatus for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation includes a multiplier, adder/subtractor and shifter each having a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.
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