公开(公告)号：EP0394499A4

公开(公告)日：1993-02-24

申请号：EP89912134

申请日：1989-11-02

申请人： HITACHI, LTD. ,  HITACHI ENGINEERING CO., LTD.

发明人： NARITA, MASAHISA ,  KAZIWARA, HISASHI ,  ASAI, TAKESHI ,  MORINAGA, SHIGEKI ,  KIDA, HIROYUKI ,  WATABE, MITSURU ,  NAKAMIKAWA, TETSUAKI ,  KAWASAKI, SHUNPEI ,  TATEZAKI, JUNICHI ,  NAKAGAWA, NORIO ,  KASHIWAGI, YUGO

IPC分类号： G06F7/52 ,  G06F7/552 ,  G06F7/57

CPC分类号： G06F7/57 ,  G06F7/4873 ,  G06F7/49957 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/3816 ,  G06F2207/5355 ,  G06F2207/5356

摘要： An apparatus for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation includes a multiplier, adder/subtractor and shifter each having a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.