发明公开
EP0401716A2 High voltage complementary NPN/PNP process
失效
Verfahren zur Herstellung vonkomplementärenNPN / PNP hoher Spannung。
- 专利标题： High voltage complementary NPN/PNP process
- 专利标题（中）： Verfahren zur Herstellung vonkomplementärenNPN / PNP hoher Spannung。
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申请号： EP90110523.9申请日： 1990-06-02
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公开(公告)号： EP0401716A2公开(公告)日： 1990-12-12
- 发明人: Jennings, Dean , Buynoski, Matthew
- 申请人： NATIONAL SEMICONDUCTOR CORPORATION
- 申请人地址： 2900 Semiconductor Drive P.O. Box 58090 Santa Clara California 95051-8090 US
- 专利权人： NATIONAL SEMICONDUCTOR CORPORATION
- 当前专利权人： NATIONAL SEMICONDUCTOR CORPORATION
- 当前专利权人地址： 2900 Semiconductor Drive P.O. Box 58090 Santa Clara California 95051-8090 US
- 代理机构： Sparing Röhl Henseler Patentanwälte
- 优先权： US361171 19890606
- 主分类号： H01L21/331
- IPC分类号： H01L21/331
摘要：
A process is disclosed for forming high-performance, high voltage PNP and NPN power transistors in a conventional monolithic, planar, epitaxial PNP junction isolated integrated circuit. The process permits independently optimizing the NPN and PNP power transistors. Where high-voltage devices are desired a field threshold adjustment implant is applied. It also includes provisions for testing critical portions of the process at appropriate points.
公开/授权文献
- EP0401716B1 High voltage complementary NPN/PNP process 公开/授权日：1996-03-06
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