公开(公告)号：EP2589055A2

公开(公告)日：2013-05-08

申请号：EP11810082.5

申请日：2011-06-27

申请人： National Semiconductor Corporation

发明人： FRENCH, William ,  HOPPER, Peter, J. ,  SMEYS, Peter ,  GABRYS, Ann ,  ANDERSON, David, I.

IPC分类号： H01F38/40 ,  H01L25/00

摘要： An integrated circuit die system comprises a first integrated circuit die, a second integrated circuit die and a transformer formed on a dielectric (e.g., quartz) substrate and electrically connected between the first integrated circuit die and the second integrated circuit die to provide galvanic isolation therebetween.

公开(公告)号：EP2487999A1

公开(公告)日：2012-08-15

申请号：EP11305130.4

申请日：2011-02-09

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Avenel, Jean-Jacques

IPC分类号： H05B37/03 ,  H05B33/08

CPC分类号： H05B33/089 ,  H05B37/032

摘要： A method includes receiving a first voltage from a first node associated with a first string (204a) of multiple light emitting diodes (LEDs) (202). The method also includes receiving a second voltage from a second node associated with a second string (204b) of multiple LEDs. The method further includes identifying whether at least one of the LEDs has a fault using the first and second voltages. Identifying whether at least one of the LEDs has a fault could include comparing a difference ( VD IFF ) between the first and second voltages to a threshold. Identifying whether at least one of the LEDs has a fault could also include determining whether a difference between the first and second voltages falls within a voltage range defined by higher and lower voltage limits (V REF +V TH , V REF -V TH) .

摘要翻译： 一种方法，包括：接收从与多个发光二极管（LED）的第一串（204A）相关联（202）的第一节点的第一电压。 因此，该方法包括：接收从与多个LED的第二串（204B）相关联的第二节点的第二电压。 该方法包括进一步的标识是否所述LED中的至少一个具有使用所述第一和第二电压中的故障。 标识是否所述LED中的至少一个具有故障可能包括在第一和第二电压之间的差（VD IFF）与阈值比较。 标识是否所述LED中的至少一个具有故障可能因此包括确定性采矿是否在第一和第二电压之间的差，如果通过较高和较低的电压极限（V REF + V TH，V REF -V TH）所定义的电压范围内。

公开(公告)号：EP2487998A1

公开(公告)日：2012-08-15

申请号：EP11305129.6

申请日：2011-02-09

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Avenel, Jean-Jacques

IPC分类号： H05B37/03 ,  H05B33/08

CPC分类号： H05B33/089 ,  H05B37/036

摘要： A method includes receiving a first voltage from an intermediate node (118) in a string (104) of multiple light emitting diodes (LEDs) (102). The method also includes receiving at least one second voltage based on a string voltage (V LED ) across the string of LEDs. The method further includes identifying whether at least one of the LEDs has a fault using the first voltage and the at least one second voltage. The second voltage could be a single reference voltage, and a difference between the first voltage and the reference voltage could be compared to a threshold. Multiple second voltages could define a voltage range that includes a reference voltage, and a determination could be made whether the first voltage falls within the voltage range.

摘要翻译： 一种方法，包括：从在的多个发光二极管（LED）的字符串（104）的中间节点（118）（102）接收第一电压。 因此，该方法包括：基于一个串电压（V LED）横跨LED串接收至少一个第二电压。 该方法包括进一步的标识是否所述LED中的至少一个具有使用所述第一电压和所述至少一个第二电压中的故障。 第二电压可以是单个参考电压，并且所述第一电压和所述基准电压之间的差可以是与阈值比较。 多个第二电压可以定义的电压范围内做了包括参考电压，并确定可以作出是否与所述第一电压，如果电压范围内。

公开(公告)号：EP2412027A1

公开(公告)日：2012-02-01

申请号：EP10756486.6

申请日：2010-03-25

申请人： National Semiconductor Corporation

发明人： BULUCEA, Constantin ,  BAHL, Sandeep, R. ,  FRENCH, William, D. ,  ARCHER, Donald, M. ,  PARKER, D., Courtney ,  CHAPARALA, Prasad ,  Yang, Jeng-Jiun

IPC分类号： H01L29/78

CPC分类号： H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (IGFETs), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

公开(公告)号：EP2412015A1

公开(公告)日：2012-02-01

申请号：EP10756492.4

申请日：2010-03-25

申请人： National Semiconductor Corporation

发明人： PARKER, D., Courtney ,  ARCHER, Donald, M. ,  BAHL, Sandeep, R. ,  BULUCEA, Constantin ,  FRENCH, William, D. ,  JOHNSON, Peter, B. ,  YANG, Jeng-Jiun

IPC分类号： H01L21/70 ,  H01L29/02 ,  H01L29/10

CPC分类号： H01L29/0847 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： A gate electrode (302) of a field-effect transistor (102) is defined above, and vertically separated by a gate dielectric layer (300) from, a channel-zone portion (284) of body material of a semiconductor body. Semiconductor dopant is introduced into the body material to define a more heavily doped pocket portion (290) using the gate electrode as a dopant-blocking shield. A spacer (304T) having a dielectric portion situated along the gate electrode, a dielectric portion situated along the body, and a filler portion (SC) largely occupying the space between the other two spacer portions is provided. Semiconductor dopant is introduced into the body to define a pair of source/drain portions (280M and 282M) using the gate electrode and spacer as a dopant-blocking shield. The filler spacer portion is removed to convert the spacer to an L shape (304). Electrical contacts (310 and 312) are formed respectively to the source/drain portions.

公开(公告)号：EP2359173A1

公开(公告)日：2011-08-24

申请号：EP09836560.4

申请日：2009-09-11

申请人： National Semiconductor Corporation

发明人： DARBINYAN, Artur ,  NGUYEN, Luu ,  PODDAR, Anindya

IPC分类号： G02B6/12 ,  G02B6/42

CPC分类号： G02B6/4214 ,  G02B6/4232

摘要： Optoelectronic packages and wafer level techniques for forming optoelectronic packages are described. In accordance with one apparatus aspect of the invention, a pair of substrates are bonded together to form an optical coupler. A first one of the substrates has a recess that faces the second substrate to at least in part define a channel suitable for receiving an optical transmission medium. A photonic device is mounted on a mounting surface of the second substrate that is opposite its bonded surface. The photonic device faces the reflective surface and an optical path is formed between the channel and the photonic element that both reflects off of the reflective surface and passes through the second substrate. In some embodiments an integrated circuit device and/or solder bumps are also attached to the mounting surface and the second substrate has conductive traces thereon that electrically couple the various electrical components as appropriate (e.g., the photonic device, the integrated circuit device, the solder bumps and/or other components). The substrates may be formed from a wide variety of materials including, glass, plastic and silicon. In some embodiments, at least the second substrate is formed from an optically transparent material and the optical path passes directly though the optically transparent material. In a method aspect of the invention, a variety of wafer level methods for forming such devices are described.

公开(公告)号：EP2291899A2

公开(公告)日：2011-03-09

申请号：EP09747632.9

申请日：2009-05-14

申请人： National Semiconductor Corporation

发明人： ZHANG, Jianhui ,  DJABBARI, Ali ,  LISI, Gianpaolo

IPC分类号： H02J7/35 ,  H02M7/48

CPC分类号： H02J3/383 ,  G05F1/67 ,  H02J3/385 ,  H02S50/00 ,  Y02E10/563 ,  Y02E10/58

摘要： A method for selecting between centralized and distributed maximum power point tracking in an energy generating system (500) is provided. The energy generating system (500) includes a plurality of energy generating devices (502), each of which is coupled to a corresponding local converter (504). Each local converter (504) includes a local controller (508) for the corresponding energy generating device (502). The method includes determining whether the energy generating devices (502) are operating under quasi-ideal conditions. The energy generating system (500) is placed in a centralized maximum power point tracking (CMPPT) mode when the energy generating devices (502) are operating under quasi-ideal conditions and is placed in a distributed maximum power point tracking (DMPPT) mode when the energy generating devices (502) are not operating under quasi-ideal conditions.

公开(公告)号：EP2291897A2

公开(公告)日：2011-03-09

申请号：EP09747617.0

申请日：2009-05-14

申请人： National Semiconductor Corporation

发明人： ZHANG, Jianhui ,  DJABBARI, Ali ,  LISI, Gianpaolo

IPC分类号： H02J7/35 ,  H02M7/48

CPC分类号： G05F1/67

摘要： A method for providing a maximum power point tracking (MPPT) process for an energy generating device (202) is provided. The method includes coupling a local converter (204) to the energy generating device (202). A determination is made regarding whether the local converter (204) is operating at or below a maximum acceptable temperature. A determination is made regarding whether at least one current associated with the local converter (204) is acceptable. When the local converter (204) is determined to be operating at or below the maximum acceptable temperature and when the at least one current associated with the local converter (204) is determined to be acceptable, the MPPT process is enabled within the local converter (204).

公开(公告)号：EP1618546A2

公开(公告)日：2006-01-25

申请号：EP04750530.0

申请日：2004-04-21

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： LUDDEN, Christopher, A.

IPC分类号： G09G1/00

CPC分类号： G09G3/3614 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2310/0224 ,  G09G2310/0289 ,  G09G2330/021

摘要： A method is arranged to process a frame for an LCD with a modified polarity pattern. The pattern employs a polarity reversal scheme that results in line inversion and/or dot inversion patterns that are observable by pixel locations within the frame. The drive polarity for the column drivers in the LCD is toggled according to the modified polarity pattern. The scanning sequence for each row on the display is modified for cooperation with the pattern. A first subframe is scanned during a first interval while applying a first set of drive polarities. A second subframe is scanned during a second interval that is non-overlapping with the first time interval. The application of the method enables the column drivers in the LCD to operate with reduced power while retaining the benefits of line and dot inversion techniques.

公开(公告)号：EP1225514A3

公开(公告)日：2005-10-12

申请号：EP02004719.7

申请日：1996-05-16

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Ballachino, William E. ,  Colgan, James A. ,  Jacobelli, Franco

IPC分类号： G06F13/38

CPC分类号： G06F13/38 ,  G06F13/385

摘要： A bidirectional parallel signal interface for providing a parallel data interface between a computer and an external peripheral device includes an interface circuit with command registers for communicating commands and data, a first-in, first-out (FIFO) memory for communicating data between the computer and the peripheral device, and host and slave state machines for receiving commands from the command registers and in accordance therewith controlling communication of data between the FIFO and peripheral device and communicating control signals to and from the peripheral device. The communication of data between the FIFO and peripheral device is effected in accordance with the commands from the command registers. The communications of control signals by the host and slave state machines are responsive to their control signals with such responsiveness being control controllable in accordance with the commands from the command registers. The communication of data from the FIFO to the peripheral device is halted by the host state machine in accordance with its commands from the command registers. The command registers include a status register for storing data from the peripheral device representing a number of status states of the peripheral device.