A digital data processing system includes a plurality of central processor units (40A, 40B, 40C) which share and access a common memory (44A, 44B, 44C) through a memory management element (46) . The memory management element permits, inter alia, data in the common memory to be accessed in at least two modes. In the first mode, all central processing units requesting access to a given datum residing in memory are signalled of the datums existence. In the second mode, only selected central processing units requesting access to a resident datum are notified that it exists, while others requesting access to the datum are signalled that it does not exist. The common memory can include a plurality of independent memory elements (44A, 44B, 44C) each coupled to and associated with, a respective one of the central processing units. A central processing unit can include a post-store element for effecting the transfer of copies of data stored in its associated memory element to a memory element associated with another central processing unit.