Improved multiprocessor system
    3.
    发明公开
    Improved multiprocessor system 失效
    Multiprozessorsystem。

    公开(公告)号:EP0404560A2

    公开(公告)日:1990-12-27

    申请号:EP90306777.5

    申请日:1990-06-21

    IPC分类号: G06F15/16 G06F12/08

    摘要: A digital data processing system includes a plurality of central processor units (40A, 40B, 40C) which share and access a common memory (44A, 44B, 44C) through a memory management element (46) . The memory management element permits, inter alia, data in the common memory to be accessed in at least two modes. In the first mode, all central processing units requesting access to a given datum residing in memory are signalled of the datums existence. In the second mode, only selected central processing units requesting access to a resident datum are notified that it exists, while others requesting access to the datum are signalled that it does not exist. The common memory can include a plurality of independent memory elements (44A, 44B, 44C) each coupled to and associated with, a respective one of the central processing units. A central processing unit can include a post-store element for effecting the transfer of copies of data stored in its associated memory element to a memory element associated with another central processing unit.

    摘要翻译: 数字数据处理系统包括通过存储器管理元件(46)共享和访问公共存储器(44A,44B,44C)的多个中央处理器单元(40A,40B,40C)。 存储器管理元件尤其允许以至少两种模式访问公共存储器中的数据。 在第一模式中,请求访问驻留在存储器中的给定数据的所有中央处理单元用信号表示基准存在。 在第二模式中,只有请求访问驻留数据的所选择的中央处理单元被通知其存在,而请求访问基准的其他中央处理单元被发信号通知其不存在。 公共存储器可以包括多个独立存储器元件(44A,44B,44C),每个独立存储器元件耦合到相应的一个中央处理单元并与之相关联。 中央处理单元可以包括用于实现将存储在其关联的存储器元件中的数据的副本传送到与另一中央处理单元相关联的存储元件的后存储元件。

    Improved multiprocessor system
    7.
    发明公开
    Improved multiprocessor system 失效
    改进的多处理器系统

    公开(公告)号:EP0404560A3

    公开(公告)日:1992-08-05

    申请号:EP90306777.5

    申请日:1990-06-21

    IPC分类号: G06F15/16 G06F12/08

    摘要: A digital data processing system includes a plurality of central processor units (40A, 40B, 40C) which share and access a common memory (44A, 44B, 44C) through a memory management element (46) . The memory management element permits, inter alia, data in the common memory to be accessed in at least two modes. In the first mode, all central processing units requesting access to a given datum residing in memory are signalled of the datums existence. In the second mode, only selected central processing units requesting access to a resident datum are notified that it exists, while others requesting access to the datum are signalled that it does not exist. The common memory can include a plurality of independent memory elements (44A, 44B, 44C) each coupled to and associated with, a respective one of the central processing units. A central processing unit can include a post-store element for effecting the transfer of copies of data stored in its associated memory element to a memory element associated with another central processing unit.