The present invention operates by verifying correct latch operation in a digital circuit. After a value has been stored in a latch, electronic circuitry can verify that the value has been stored correctly. The electronic circuitry that performs this verification can be tested to insure that it is operating properly. Several latches can be wired into a scan chain and tested with relative ease. Operation of the present invention is illustrated by an enhanced master-slave latch system. In this system, two comparators are used. A first comparator (308) is used to determine if the internal state of the master latch is identical to the signal which had been applied to this latch's data input terminal (Q₁). A second comparator (310) is used to determine if the state transfer between the master (305) and slave (306) latches occurs properly. Each comparator consists of an EXCLUSVIE-OR function. By placing known logic levels on each input terminal of the comparison circuitry, the output terminal of the comparison circuitry can be examined for an expected logic level to verify that it is operating properly. By placing several latches into a scan chain (719) , a single latch can be loaded with data which will cause an expected signal to appear on the output terminal of this latch's comparison circuitry. This allows for simplified testing of a multiple latch system.