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1.发明公开Apparatus for determining if there is a loss of data during a shift operation 失效Gerätum festzustellen，obwährendeiner Verschiebungsoperation Daten in Verlust geraten。
公开(公告)号：EP0377845A2
公开(公告)日：1990-07-18
申请号：EP89122989.0
申请日：1989-12-13
CPC分类号： G06F5/015 , G06F7/49952
摘要： Apparatus for shifting and determining if during the shifting of data there has been a loss of precision due to the loss of one or more data bits due to overflow. A small data field is shifted into a much larger data field. The width of the switching mechanism used is based on the number of bits in the small data field. Loss of data is determined in part by ORing the control signals utilized to shift the small data field to the large data field.
摘要翻译： 用于移位和确定在数据移位期间是否由于溢出导致的一个或多个数据位的丢失而导致精度损失的装置。 一个小数据字段被转移到一个更大的数据字段。 所使用的切换机制的宽度是基于小数据字段中的位数。 通过将用于将小数据字段移位到大数据字段的控制信号进行OR运算来部分地确定数据丢失。
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公开(公告)号：EP0362580B1
公开(公告)日：1996-04-24
申请号：EP89116899.9
申请日：1989-09-13
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公开(公告)号：EP0218794B1
公开(公告)日：1990-10-17
申请号：EP86108504.1
申请日：1986-06-21
发明人： Kirkpatrick, Edward Scott , Kronstadt, Eric Paul , Montoye, Robert Kevin , Wilcke, Winfried Wolfgang
CPC分类号： G06F11/2215 , G01R31/318541 , G01R31/318572 , G01R31/31858 , G06F11/0751
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4.发明公开Floating point unit having simultaneous multiply and add 失效Gleitkommaeinheit mit gleichzeitiger Multiplikation und Addition。
公开(公告)号：EP0377837A2
公开(公告)日：1990-07-18
申请号：EP89122891.8
申请日：1989-12-12
发明人： Cocke, John , Montoye, Robert Kevin
IPC分类号： G06F7/48
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49936 , G06F7/49947
摘要： A single floating point that produces the result A x B + C with A, B and C being floating point numbers. The operand C is shifted in parallel with the beginning phases of the multiplication. The result is produced after a single addition and normalization, reducing hardware, delay and rounding errors.
摘要翻译： 产生结果的单个浮点A x B + C，A，B和C为浮点数。 操作数C与乘法的开始阶段平行移动。 结果是在单次添加和归一化后产生的，从而减少硬件，延迟和舍入误差。
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公开(公告)号：EP0362580A2
公开(公告)日：1990-04-11
申请号：EP89116899.9
申请日：1989-09-13
摘要： A method and system are disclosed for performing a leading 0/1 anticipation (LZA) in parallel with the floating-point addition of two operands (A and B) in a computer to significantly reduce the Addition-Normalization time. A combinational network is used to process appropriate XOR (P), AND (G), and NOR (Z) state signals resulting from the comparison of the bits in corresponding bit positions of the operands (A and B), starting with the most significant bit (MSB) side of the addition. The state of the initial state signal is detected and shift amount signals are produced and counted for each successive state signal detected, as long as the state remains TRUE. When the state becomes NOT TRUE, adjustments are made depending on the initial state and the successive state, and production of the shift amount signals is halted and an adjustment signal is produced. To determine the exponent of the sum of the floating-point addition, the shift amount count is summed with the adjustment signal. The latter sum will be the exponent of the sum of the operands thus providing a normalized result. The adjustment signal may be based on the CARRY at the NOT TRUE bit position, and the state at the NOT TRUE position may be used to determine whether the result of the addition is positive or negative.
In addition to a serial network, an implementing network of a parallel form which accepts appropriate state inputs as blocks of n bits in length, is disclosed, along with certain special implementation.摘要翻译： 公开了用于在计算机中与两个操作数（A和B）的浮点加法并行地执行前导0/1预期（LZA）以显着减少加法 - 归一化时间的方法和系统。 组合网络用于处理从操作数（A和B）的相应位位置中的位的比较产生的适当XOR（P），AND（G）和NOR（Z）状态信号，从最高有效 位（MSB）侧的加法。 检测到初始状态信号的状态，并且只要状态保持为TRUE，就为每个检测到的连续状态信号产生和计数移位量信号。 当状态不为真时，根据初始状态和连续状态进行调整，停止偏移量信号的产生并产生调整信号。 为了确定浮点加法和的指数，移位量计数与调整信号相加。 后一个和将是操作数之和的指数，从而提供归一化结果。 调整信号可以基于在NOT TRUE位位置处的CARRY，并且可以使用NOT TRUE位置处的状态来确定添加的结果是正还是负。 除了串行网络之外，还公开了一种并行形式的实现网络，其接受适当状态输入作为长度为n位的块，以及某些特殊实现。
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公开(公告)号：EP0218794A1
公开(公告)日：1987-04-22
申请号：EP86108504.1
申请日：1986-06-21
发明人： Kirkpatrick, Edward Scott , Kronstadt, Eric Paul , Montoye, Robert Kevin , Wilcke, Winfried Wolfgang
CPC分类号： G06F11/2215 , G01R31/318541 , G01R31/318572 , G01R31/31858 , G06F11/0751
摘要： An improved testing and checking circuit for a Differential Cascode Voltage Switch which uses N-devices for both the invalid (0.0) and (1.1) state detection of Q and Q switch signals, and uses decoupling pass devices for sampling the data at the fall of the system C-clock, additionally allowing simultaneous pre-charging and error detection. The testing and checking circuit is incorporated in a hierarchical scheme, which uses the system C-clock for input to the latches, decoupling of the buffers, and pulling up and down the error lines. The error fault is held in a system latch. Also described is a circuit scheme which self tests a large macro using only the C-clock and latches the result in a single latch. More particularly, the described circuit employs the Q and Q signals in a NOR configuration circuit 30, 32, 34, thus detecting if neither signal has sufficient voltage to pull down the load device 34 which consists of a P-device whose gate is attached to the C-clock. The resulting signal is run to a gate 44 in parallel with the two N-devices 44, 46. Thus, the two low signals allow this NOR gate to rise and produce a pulldown leg to an error line 24. An invalid signal condition is detected if either both signals are sufficiently high to turn on an N-device or neither signal is high enough to turn on N-devices 46, 48. Therefore, the described circuit registers a failure if and only if there is the potential for a tree with the same inputs to enter an invalid state.
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公开(公告)号：EP0377837B1
公开(公告)日：1995-10-04
申请号：EP89122891.8
申请日：1989-12-12
发明人： Cocke, John , Montoye, Robert Kevin
IPC分类号： G06F7/48
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49936 , G06F7/49947
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8.发明公开Apparatus for determining if there is a loss of data during a shift operation 失效如果在移位操作期间数据丢失，则可以进行确定
公开(公告)号：EP0377845A3
公开(公告)日：1992-05-13
申请号：EP89122989.0
申请日：1989-12-13
CPC分类号： G06F5/015 , G06F7/49952
摘要： Apparatus for shifting and determining if during the shifting of data there has been a loss of precision due to the loss of one or more data bits due to overflow. A small data field is shifted into a much larger data field. The width of the switching mechanism used is based on the number of bits in the small data field. Loss of data is determined in part by ORing the control signals utilized to shift the small data field to the large data field.
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公开(公告)号：EP0418521A2
公开(公告)日：1991-03-27
申请号：EP90114663.9
申请日：1990-07-31
CPC分类号： G06F11/2215 , G01R31/318525 , G11C29/32
摘要： The present invention operates by verifying correct latch operation in a digital circuit. After a value has been stored in a latch, electronic circuitry can verify that the value has been stored correctly. The electronic circuitry that performs this verification can be tested to insure that it is operating properly. Several latches can be wired into a scan chain and tested with relative ease. Operation of the present invention is illustrated by an enhanced master-slave latch system. In this system, two comparators are used. A first comparator (308) is used to determine if the internal state of the master latch is identical to the signal which had been applied to this latch's data input terminal (Q₁). A second comparator (310) is used to determine if the state transfer between the master (305) and slave (306) latches occurs properly. Each comparator consists of an EXCLUSVIE-OR function. By placing known logic levels on each input terminal of the comparison circuitry, the output terminal of the comparison circuitry can be examined for an expected logic level to verify that it is operating properly. By placing several latches into a scan chain (719) , a single latch can be loaded with data which will cause an expected signal to appear on the output terminal of this latch's comparison circuitry. This allows for simplified testing of a multiple latch system.
摘要翻译： 本发明通过验证数字电路中的正确的锁存器操作来操作。 一个值存储在锁存器中之后，电子电路可以验证该值是否已被正确存储。 可以测试执行此验证的电子电路，以确保其正常运行。 几个闩锁可以连接到扫描链中并相对容易地进行测试。 通过增强的主 - 从锁存系统来说明本发明的操作。 在这个系统中，使用两个比较器。 第一比较器（308）用于确定主锁存器的内部状态是否与施加到该锁存器的数据输入端子（Q1）的信号相同。 第二比较器（310）用于确定主（305）和从（306）锁存器之间的状态传输是否正确发生。 每个比较器由EXCLUSVIE-OR功能组成。 通过将已知的逻辑电平置于比较电路的每个输入端上，可以检查比较电路的输出端以获得期望的逻辑电平，以验证它是否正常工作。 通过将多个锁存器放入扫描链（719），单个锁存器可以加载数据，这将导致预期信号出现在该锁存器比较电路的输出端子上。 这允许简化的多重锁定系统的测试。
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10.发明公开Apparatus for performing floating point arithmetic operations 失效GerätzumAusführenarithmetischer Gleitkommaoperationen。
公开(公告)号：EP0377994A2
公开(公告)日：1990-07-18
申请号：EP89313405.6
申请日：1989-12-20
IPC分类号： G06F7/48
CPC分类号： G06F9/3889 , G06F7/483 , G06F7/49947 , G06F7/5443
摘要： A processor for performing floating point arithmetic operations includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.
摘要翻译： 用于进行浮点算术运算的处理器包括对第一周期中的一组操作数执行第一个浮点算术运算的电路和一个操作数上的第二个浮点算术运算，以及一个运算的第一个浮点算术运算的结果 第二个循环。 提供一种控制电路，用于在第三个周期内将第二浮动操作的结果传送到第一浮点运算，用于在下一个连续循环中进行第一浮点运算，同时舍入第二浮点运算的结果。
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