The wafer scale integrated circuit arises an array of undiced chips or modules 10, each of which includes a data storing or processing circuit, e.g. a dyamic RAM, and configuration logic. Channels 11 for data and control signals exists between each module and its N, S, E, and W neighbours and a target module in the array may be addressed by setting up a path 12 through the array from an entry module to the target module. To address a target module the link commands are transmitted from module to module in parallel, each module responds to the command at the least significant end and strips it off by a shift of the bands in the least significant direction before the commands pass to the next module. A control circuit for addressing modules in the array at random forms a unique set of link cob for each module to be addressed, these command sets being such that the paths to the various modules form a densely branching tree commencing from the entry module.