The process of synchronization and decomposition of asynchronous frames organized with octet-rows of bits, for the adaptation of speed carried out by an intermediate reception block for adaptation of speed of an integrated device for the adaptation of synchronous and asynchronous terminals according to the CCITT V.110 standard to an Integrated Services Digital Network, is carried out by storing one octet at a time in an 8-bit shift register (RSC8) and by using counters (RSA,RSB,RSC8) in order to store the current position of each octet within a respective asynchronous frame and by recognizing by means of other counters (CT80,CTNFR) the relevant bits of each octet, which are stored and switched to the respective elements for management and for control of the serial flow of data from the network to the terminal. From this, an architecture is derived, which is particularly simplified by means of the redimensioning of the registers which, instead of storing an entire frame, have to store only one octet at a time. Also, the delay undergone by the data in transfer by means of the block is reduced to the delay necessary for the shifting of a single octet. In fact, there will never be more than two octets at a time contained within the block instead of two frames or one, as would be necessary according to an architecture of conventional type. Two PLAs (RS2,RS3), each functioning with its own clock (CK0,CK1), manage and control the synchronization, the decomposition of the frames into octets and the addressing of the bits and, respectively, the flow of the data in input to and in output from the block in relation to said standard.