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1.发明公开Process for forming an edge structure to seal integrated electronic devices, and corresponding device 失效一种用于边缘结构的集成电子器件的制备过程中被密封，并且相对应的设备
公开(公告)号：EP0856886A1
公开(公告)日：1998-08-05
申请号：EP97830029.1
申请日：1997-01-31
发明人： Calegari, Camilla , Carrara, Anna , Fratin, Lorenzo , Riva, Carlo
IPC分类号： H01L23/00 , H01L23/532
CPC分类号： H01L23/564 , H01L23/3171 , H01L23/5329 , H01L2924/0002 , Y10S438/958 , H01L2924/00
摘要： A process for the formation of a device edge morphological structure (30) for protecting and sealing peripherally an electronic circuit integrated in a major surface (5) of a substrate of semiconductor material (6) is of the type that calls for formation above the major surface (5) of at least one dielectric multilayer (20) comprising a layer of amorphous planarizing material (22) having a continuous portion extending between two contiguous areas with a more internal first area (3') and a more external second area (4') in the morphological structure (30).
In accordance with the present invention inside the device edge morphological structure (30) in the substrate (6) is formed an excavation on the side of the major surface (5) the more internal first area (3') of the morphological structure (30) in a zone in which is present the continuous portion of the dielectric multilayer (20).摘要翻译： 为集成在一个主表面的电子电路的保护和密封经外周为一个装置边缘的形态结构（30）的形成的方法，（5）的半导体材料的基片（6）是所述类型的那样呼叫为了形成上述的主要 至少一个电介质多层（20），包括无定形的平坦化材料的具有连续的部分中的两个相邻的区域之间延伸的具有多个内部第一区域（3“）的层（22）和多个外部的第二区域的表面（5）（4 “）（在形态结构30）。 在与在器件边缘的形态结构（30）内的本发明雅舞蹈的（6）在主表面的形态结构的侧面（5）的更内部的第一区域（3”）而形成的挖掘（30个基板 ）（在所有的区域，其存在于电介质多层20）的连续部分。
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公开(公告)号：EP0855788A1
公开(公告)日：1998-07-29
申请号：EP97830014.3
申请日：1997-01-23
IPC分类号： H02M3/07
CPC分类号： H02M3/073
摘要： A negative charge pump circuit comprises a plurality of charge pump stages (S1'-S4') connected in series to each other. Each stage has a stage input terminal (SI) and a stage output terminal (SO). A first stage (S1') has the stage input terminal (SI) connected to a reference voltage, a final stage (S4') has the stage output terminal (SO) operatively connected to an output terminal (O) of the charge pump at which a negative voltage is developed; intermediate stages (S2' ,S3') have the respective stage input terminal (SI) connected to the stage output terminal (SO) of a preceding stage and the respective stage output terminal connected to the stage input terminal of a following stage. Each stage (S1'-S4') comprises a first N-channel MOSFET (M1') with a first electrode connected to the stage input terminal (SI) and a second electrode connected to the stage output terminal (SO), a second N-channel MOSFET (M2') with a first electrode connected to the stage output terminal (SO) and a second electrode connected to a gate electrode of the first N-channel MOSFET (M1'), a boost capacitor (CP) with one terminal connected to the gate electrode of the first N-channel MOSFET and a second terminal driven by a respective first digital signal (A',C') switching between the reference voltage and a positive voltage supply (VDD), and a second capacitor (CL) with one terminal connected to the charge pump stage output terminal (SO) and a second terminal connected to a respective second digital signal (B',D') switching between the reference voltage and the voltage supply (VDD). A gate electrode of the second N-channel MOSFET (M2') is connected, in the first stage (S1'), to a third digital signal (D') switching between the reference voltage and the voltage supply, while in the remaining stage the gate electrode of the second N-channel MOSFET is connected to the stage input terminal (SI).
摘要翻译： 负电荷泵电路包括彼此串联连接的多个电荷泵级（S1'-S4'）。 每个级具有级输入端（SI）和级输出端（SO）。 第一级（S1'）具有连接到参考电压的级输入端（S1），最后级（S4'）使级输出端（SO）可操作地连接到电荷泵的输出端（O） 开发出负电压; 中间级（S2'，S3'）具有连接到前一级的级输出端（SO）的各级输入端（SI）和连接到后级的级输入端的各级输出端。 每个级（S1'-S4'）包括第一N沟道MOSFET（M1'），其中第一电极连接到级输入端（SI），第二电极连接到级输出端（SO），第二N - 沟道MOSFET（M2'），第一电极连接到平台输出端子（SO），第二电极连接到第一N沟道MOSFET（M1'）的栅电极，升压电容器（CP） 连接到第一N沟道MOSFET的栅电极和由在基准电压和正电压源（VDD）之间切换的相应的第一数字信号（A'，C'）驱动的第二端子和第二电容器（CL ），一个端子连接到电荷泵级输出端子（SO），第二端子连接到在参考电压和电压源（VDD）之间切换的相应的第二数字信号（B'，D'）。 第二N沟道MOSFET（M2'）的栅电极在第一级（S1'）中连接到在参考电压和电压源之间切换的第三数字信号（D'），而在剩余级 第二N沟道MOSFET的栅电极连接到级输入端（SI）。
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3.发明授权
公开(公告)号：EP0463418B1
公开(公告)日：1998-07-29
申请号：EP91109162.7
申请日：1991-06-05
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4.发明授权EPROM cell with a readily scalable down interpoly dielectric 失效多晶硅层之间的EPROM单元Dielektricum，这是容易制造在小尺寸的
公开(公告)号：EP0571692B1
公开(公告)日：1998-07-22
申请号：EP92830266.0
申请日：1992-05-27
CPC分类号： H01L29/511 , Y10S148/114
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5.发明公开
公开(公告)号：EP0851585A1
公开(公告)日：1998-07-01
申请号：EP96830650.6
申请日：1996-12-24
发明人： Milanesi, Andrea
IPC分类号： H03K17/284 , H03K17/14 , G05F3/24
CPC分类号： H03K17/284 , G05F3/242
摘要： A circuit for the generation of an electrical signal of constant duration comprises a capacitor (C), a constant current generator for charging said capacitor and a voltage comparator (COMP) to compare the voltage present at the terminals of the capacitor with a reference voltage (V ref ) and supply at output a digital signal (OUT) dependent upon the voltage across the capacitor; the constant current generator comprises a transistor (M1) biased with a voltage (V gsx) between gate and source obtained as the difference between the sum of two gate-source voltages of two transistors (M2,M3) and a gate-source voltage of another transistor (M4).
摘要翻译： 一种用于恒定的持续时间的电气信号的发生电路包括一个电容器（C），恒流发生器，用于充电所述电容器和一个电压比较器（COMP）比较存在于电容器的与基准电压端子处的电压（ V REF）和电源在输出的数字信号（OUT）取决于电容器两端的电压; 恒定电流发生器包括晶体管（M1）被偏置以获得作为两个晶体管（M2，M3）和另一个的栅 - 源电压的两个栅极 - 源极电压的总和之间的差的栅极和源极之间的电压（Vgsx） 晶体管（M4）。
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6.发明公开N-Channel MOS transistor with NO LDD junction and corresponding manufacturing method 失效N-Kanal-MOS晶体管Ohne LDD-Übergangund entsprechende Herstellungsmethode
公开(公告)号：EP0851495A1
公开(公告)日：1998-07-01
申请号：EP96830647.2
申请日：1996-12-24
IPC分类号： H01L27/105 , H01L29/08
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： The invention relates to an N-channel MOS transistor structure having a NO LDD junction, and to a manufacturing process therefor.
The transistor is of the type which is incorporated into CMOS structures of electronic memory devices (2) integrated on a semiconductor substrate (3) and comprising a plurality of memory cells (2), each cell being comprised of a floating gate transistor (11) with active areas (5) formed on the substrate (3) laterally of the gate region (11). The transistor has source (15) and/or drain (11) regions formed on the substrate (3) at adjacent locations to the locations of the active areas (5) of the memory cell (2).摘要翻译： 本发明涉及具有NO LDD结的N沟道MOS晶体管结构及其制造方法。 该晶体管是并入到集成在半导体衬底（3）上并且包括多个存储单元（2）的电子存储器件（2）的CMOS结构中的类型，每个单元由浮栅晶体管（11）组成， 其中在所述栅极区域（11）的横向上形成在所述基板（3）上的有源区域（5）。 晶体管具有在存储单元（2）的有源区（5）的相邻位置处在衬底（3）上形成的源极（15）和/或漏极（11）区域。
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7.发明公开Process for deposing a stratified dielectric for enhancing the planarity of semiconductor electronic devices 失效沉积多层介电，以提高电子的半导体电路的平面的方法，
公开(公告)号：EP0851470A1
公开(公告)日：1998-07-01
申请号：EP96830645.6
申请日：1996-12-24
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/316
CPC分类号： H01L21/76819 , H01L21/31056 , H01L21/316
摘要： A plurality of bit lines (6) are isolated from one another by a layered dielectric structure to provide a planar architecture onto which an optional conductive layer may be deposited.
The dielectric structure deposited with the method proposed in the instant Patent Application uses a highly planarizing dielectric layer (18) of the SOG type spun over a first insulating dielectric layer (17) and then solidified by means of a thermal polymerization process. The dielectric layers (17,18) are subjected to a etch-back treatment and to a subsequent thermal annealing treatment.摘要翻译： 的位线的多个（6）彼此隔离由多层介电结构提供一种平面结构走上选择性设置的导电层的哪个可被沉积。 在本专利申请中提出的方法沉积在介电结构采用旋涂在第一电介质绝缘层（17），然后通过热聚合工艺来固化SOG的类型的高平坦化介电层（18）。 介电层（17,18）经受一个回蚀刻处理和随后的热退火处理。
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8.发明公开Coding and memorizing method for fuzzy logic rules and circuit architecture for processing such rules 失效对模糊逻辑规则和电路架构用于处理这样的规则编码和存储方法
公开(公告)号：EP0851342A1
公开(公告)日：1998-07-01
申请号：EP96830656.3
申请日：1996-12-27
IPC分类号： G06F7/00
CPC分类号： G06N7/04
摘要： The invention relates to a method of coding and storing fuzzy logic rules, and to a circuit architecture for processing such rules.
The method provides for at least one inference rule of the IF/THEN type, having a predetermined number of antecedent parts (A,B,C...) of fuzzy variables and at least one consequent part (Z), to be dismembered and stored into memory words (10) to allow of subsequent processing using logic operators of the AND/OR/NOT type. The coding of rules and variables is effected sequentially. Thus, the occupation of memory locations can be minimized.
Specifically, the rules are coded through a multi-word description, such that the number of words coding each rule is a varying number dependent on the number of antecedent parts in the rule.摘要翻译： 本发明涉及编码和存储模糊逻辑规则的方法，以及在电路结构，用于处理搜索规则。 该方法提供用于将IF / THEN类型中的至少一个推理规则，具有先行份（... A，B，C）模糊变量和至少一个随后的部分（Z）的预定数量的，被肢解和 存储到存储器字（10），使用的AND / OR / NOT输入逻辑运算符，以允许后续的处理。 规则和可变编码是实现按顺序。 因此，存储位置的占用可以被最小化。 具体地，规则通过一个多字描述编码，检查做字编码的每个规则的数目不同数目依赖于规则前提的部件的数量。
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公开(公告)号：EP0848307A1
公开(公告)日：1998-06-17
申请号：EP96830619.1
申请日：1996-12-11
CPC分类号： H03H17/0261 , H03H2222/02
摘要： The fuzzy filtering of a noise signal comprising a plurality of signal samples [s(t,k)] is carried out using as variables the variation of the signal in the considered window and the distance of the samples from a sample to be reconstructed, so as to distinguish the typical variations of the original signal from those due to the noise and to identify the signal fronts. The method comprises the steps of: defining a current signal sample [s(t)] from among the plurality of signal samples; calculating a plurality of difference samples [D(t,k)] as difference in absolute value between the current signal sample and each signal sample; defining distance values (k) between the current signal sample and each signal sample; determining weight parameters [P(k)] on the basis of the difference samples and the distance values by means of fuzzy logic; and weighing the signal samples with the weight parameters so as to obtain a reconstructed signal sample [o(t)].
摘要翻译： 使用包含多个信号样本Äs（t，k）Ü的噪声信号的模糊滤波使用所考虑的窗口中的信号的变化和样本与要重构的样本的距离作为变量进行，以便 以区分原始信号与由于噪声引起的信号的典型变化并识别信号前沿。 该方法包括以下步骤：从多个信号样本中定义当前信号样本Äs（t）Ü; 计算多个差分样本ÄD（t，k）Ü作为当前信号样本与每个信号样本之间的绝对值差; 定义当前信号样本和每个信号样本之间的距离值（k）; 基于差分样本和模糊逻辑的距离值确定权重参数ÄP（k）Ü; 并用权重参数称量信号样本，以便获得重建信号样本Äo（t）Ü。
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10.发明公开Method and device for suppressing parasitic effects in a junction-insulated integrated circuit 失效装置和方法，用于抑制在集成电路中具有的pn绝缘区的寄生效应
公开(公告)号：EP0847089A1
公开(公告)日：1998-06-10
申请号：EP96830614.2
申请日：1996-12-09
IPC分类号： H01L27/088 , H01L27/02
CPC分类号： H01L27/0248 , H01L27/088
摘要： The method described is applied to an integrated circuit formed on a substrate (10) of p-type material having at least one region (11) of n-type material with junction insulation, first electrical contact means (20,21) on the frontal surface of the substrate, second electrical contact means (14,14') on the n-type region (11) and third electrical contact means (8) on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact means (14,14') to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact means (20,21) are taken to the potential of the second contact means (14,14'), otherwise they are held at the (ground)potential of the reference terminal. A device and an integrated circuit which utilise the method are also described.
摘要翻译： 所描述的方法被施加到与形成于具有n型材料中的至少一个区域（11），且结绝缘，第一电接触装置（20,21）上的头的p型材料的基片（10）的集成电路 在n型区域（11）和第三电接触装置的基板，第二电接触器件（14,14“）的表面（8）上连接到所述集成电路的基准（接地）端子的基板的背面 ， 为了避免在基片的电流由于寄生双极晶体管的集成电路中，所述方法提供了用于监测所述第二接触装置（14,14“）的电势的某些操作条件的导通来检测，如果该电势从出发（ 地）通过在量高于预定阈值的参考端子的电势。 如果发生此第一接触装置（20,21）被带到第二接触装置（14,14“）的电位，否则，这些都在参考端子的（接地）电势保持。 因此，一个装置和集成电路，其利用该方法进行了描述。
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