A master slice semiconductor circuit comprising ROM memory cells which consist of NMOS-transistors as well as PMOS-­transistors. In order to increase the integration density on the master slice, the NMOS-transistors and the PMOS-transistors (memory cells) in one and the same row are controlled via one and the same word line. The circuit comprises row selection means, for example an exclusive-OR circuit for each row, for selecting either a single row of NMOS cells or a single row of PMOS cells.