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14 条记录 (耗时 0.009 秒)

    Integrated CMOS circuit
    3.
    发明公开
    Integrated CMOS circuit 失效
    Integrierte CMOS-Schaltung。

    公开(公告)号：EP0425032A1

    公开(公告)日：1991-05-02

    申请号：EP90202798.6

    申请日：1990-10-19

    申请人： Philips Electronics N.V.

    发明人： Veendrick, Hendrikus Josephius Maria ,  Van den Elshout, Andreas Antonius Johannes Maria ,  Harberts, Dirk Willem

    IPC分类号： H01L27/118

    CPC分类号： H01L27/11807

    摘要： A gate array circuit comprising a row of consecutively arranged n -channel transistors and an adjacent row of p -channel transistors. Both rows are composed of at least three subrows with two subrows of narrow transistors and one subrow of wide transistors, of which the channel width is at least three times the width of the narrow transistors. The gate electrodes are common to the three subrows. Preferably, the wide subrow is arranged centrally between the narrow subrows. This construction affords the advantage of a very high density and a very high flexibility in designing the functions to be realized.

    摘要翻译： 一种门阵列电路，包括一排连续排列的n沟道晶体管和一相邻的p沟道晶体管。 两行由至少三个具有两个子晶体的窄晶体管和一个宽晶体管的子线组成，其中沟道宽度至少为窄晶体管宽度的三倍。 栅电极对于三个子线是共同的。 优选地，宽的子行布置在狭窄的子宫之间的中心。 这种结构在设计要实现的功能方面具有非常高的密度和非常高的灵活性的优点。

    Integrated electronic multiplex circuit and integrated electronic circuit including such a multiplex circuit
    4.
    发明公开
    Integrated electronic multiplex circuit and integrated electronic circuit including such a multiplex circuit 失效
    集成电子复用电路和包括这种复用电路的集成电子电路

    公开(公告)号：EP0201128A1

    公开(公告)日：1986-12-17

    申请号：EP86200729.1

    申请日：1986-04-29

    申请人： Philips Electronics N.V.

    发明人： Pfennings, Leonardus Ch. M. G. ,  Veendrick, Hendrikus Josephius Maria ,  Van Zanten, Adrianus Teunis

    IPC分类号： H04J3/04

    摘要： The multiplex circuit inludes a cascade connection of flip-flop elements (118,120,122) for producing a high data-rate multiplexsignal. In order to avoid disturbances caused by parallel loading the flip-flop circuits, the slave-section (130) of the flip-flop generating the multiplexsignal is not parallel loaded, which results in a continuous outputsignal. This way of loading requires a specific flip-flop circuit as shown in the description.

    摘要翻译： 复用电路包括用于产生高数据速率多路复用信号的触发器元件（118,120,122）的级联连接。 为了避免由并行加载触发器电路引起的干扰，产生复用信号的触发器的从属部分（130）不是并行加载的，这导致连续的输出信号。 这种加载方式需要特定的触发器电路，如说明中所示。

    Integrated semiconductor circuit of the master slice type
    7.
    发明公开
    Integrated semiconductor circuit of the master slice type 失效
    Integrierte Halbleiterschaltung vom Master-slice-Typ。

    公开(公告)号：EP0434104A1

    公开(公告)日：1991-06-26

    申请号：EP90202962.8

    申请日：1990-11-09

    申请人： Philips Electronics N.V.

    发明人： van den Elshout, Andreas Antonius Johannes Maria ,  Veendrick, Hendrikus Josephius Maria ,  Harberts, Dirk Willem

    IPC分类号： G11C11/00 ,  G11C17/12

    CPC分类号： G11C11/005

    摘要： A master slice semiconductor circuit comprising ROM memory cells which consist of NMOS-transistors as well as PMOS-­transistors. In order to increase the integration density on the master slice, the NMOS-transistors and the PMOS-transistors (memory cells) in one and the same row are controlled via one and the same word line. The circuit comprises row selection means, for example an exclusive-OR circuit for each row, for selecting either a single row of NMOS cells or a single row of PMOS cells.

    摘要翻译： 包括由NMOS晶体管以及PMOS晶体管组成的ROM存储单元的主分片半导体电路。 为了提高母片上的积分密度，同一行中的NMOS晶体管和PMOS晶体管（存储单元）通过同一字线进行控制。 电路包括行选择装置，例如用于每行的异或电路，用于选择单行NMOS单元或单行PMOS单元。

    Multi-mode memory device
    10.
    发明公开
    Multi-mode memory device 失效
    在mehrere Betriebsarten umschaltbare Speicheranordnung。

    公开(公告)号：EP0295751A1

    公开(公告)日：1988-12-21

    申请号：EP88201219.8

    申请日：1988-06-15

    申请人： Philips Electronics N.V.

    发明人： Van Zanten, Adrianus Teunis ,  Veendrick, Hendrikus Josephius Maria ,  Steenhof, Frits Anthonie ,  Frencken, Peter Hubertus ,  Nillesen, Antonius Hendrikus Hubertus Jozef ,  van der Sanden, Cornelis Gerardus Leonardus Maria

    IPC分类号： G11C19/28

    CPC分类号： G11C19/287 ,  G11C27/04

    摘要： The invention relates to a memory device of the charge-­coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2x2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.

    摘要翻译： 本发明涉及电荷耦合移位寄存器类型的存储器件，其被细分为四个部分，每个部分具有例如208,800位的存储容量，并且可以以不同的模式操作：并行/并行输出（ 作为背景视频存储器）; 2x2并行，多路复用/多路复用模式，例如用于100 Hz电视; 扫描模式; 平行再循环模式; “缩短”内存，例如525线系统等。 通过解码和定时块实现控制，其中多位控制字被串行输入和解码。 在扫描模式（例如，作为图文电视存储器）中，存储器部分在单独的扫描寄存器的控制下逐个扫描，其中扫描位（逻辑1）被逐步移位，直到所有部分具有 已阅读 通过数据输出，扫描位例如传送到与前一个存储器件串联连接的另一存储器件（通过其串行数据输入）的扫描寄存器。