A cell signal processing circuit is provided which is capable of precisely extracting a timing signal and a cell synchronizing signal. The cell signal processing circuit is principally composed of an signal adder circuit (2) for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals, and a separator circuit (12) for separating and out-putting the time series cell signals. The dummy signal composed of the same number of bits "0" and "1" is added to input signals in the form of time series cells such that signal cells are exchanged at a time of a bit "0" in the dummy signal. An optical switch apparatus using the above-mentioned cell signal processing circuit as an optical switch array (8) is also provided which includes a photoelectric converter (9) for converting the time series optical cell signal to an electric signal, a clock recovery circuit (13) for extracting a clock signal from an output from the photoelectric converter, a cell synchronization circuit (14) for extracting a cell synchronizing signal from the output from the photoelectric converter, and a decision circuit (11) for decision the output from the photoelectric converter by the use of the clock signal. The optical switch apparatus of the invention has a simple circuit arrangement which is not influenced by data loss and jitter.