发明授权
- 专利标题: Checkpointing mechanism for fault-tolerant systems
- 专利标题(中): 检查点机制容错系统。
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申请号: EP90480021.6申请日: 1990-02-08
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公开(公告)号: EP0441087B1公开(公告)日: 1995-08-16
- 发明人: Alaiwan, Haissam , Basso, Claude , Calvignac, Jean , Combes, Jacques , Kermarec, François , Pauporte, André
- 申请人: International Business Machines Corporation
- 申请人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 代理机构: Lattard, Nicole
- 主分类号: G06F11/20
- IPC分类号: G06F11/20
摘要:
A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.
公开/授权文献
- EP0441087A1 Checkpointing mechanism for fault-tolerant systems 公开/授权日:1991-08-14
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