A source (13), a drain (14), and a channel (15) are formed in an element region of a semiconductor substrate (11). A gate electrode (16) is formed above the channel (15). An insulating oxide film (18) is deposited on the entire surface of the resultant structure. Contact holes (19) and (20) are formed to bring the source (13) and drain (14) of each memory cell transistor into contact with each other. A wiring layer of a first aluminum layer is formed on the insulating oxide film including inner portions of the contact holes (19) and (20). The wiring layer includes a wiring layer (21A) for connecting adjacent memory cell transistors and a wiring layer (21B) for short-circuiting the source (13) and drain (14) to operate a memory cell transistor in the same manner as a depletion type transistor does.