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    Read-only semiconductor memory device
    2.
    发明公开
    Read-only semiconductor memory device 失效
    努尔 - Lese酒店 - Halbleiterspeicheranordnung。

    公开(公告)号：EP0447976A1

    公开(公告)日：1991-09-25

    申请号：EP91104009.5

    申请日：1991-03-15

    申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

    发明人： Takase, Shinsuke, c/o Intellectual Property Div. ,  Tanaka, Yutaka, c/o Intellectual Property Div. ,  Hashimoto, Hisashi, c/o Intellectual Property Div.

    IPC分类号： H01L27/112

    CPC分类号： G11C17/123 ,  H01L27/112

    摘要： A source (13), a drain (14), and a channel (15) are formed in an element region of a semiconductor substrate (11). A gate electrode (16) is formed above the channel (15). An insulating oxide film (18) is deposited on the entire surface of the resultant structure. Contact holes (19) and (20) are formed to bring the source (13) and drain (14) of each memory cell transistor into contact with each other. A wiring layer of a first aluminum layer is formed on the insulating oxide film including inner portions of the contact holes (19) and (20). The wiring layer includes a wiring layer (21A) for connecting adjacent memory cell transistors and a wiring layer (21B) for short-circuiting the source (13) and drain (14) to operate a memory cell transistor in the same manner as a depletion type transistor does.

    摘要翻译： 源极（13），漏极（14）和沟道（15）形成在半导体衬底（11）的元件区域中。 栅极（16）形成在通道（15）的上方。 绝缘氧化膜（18）沉积在所得结构的整个表面上。 形成接触孔（19）和（20）以使每个存储单元晶体管的源极（13）和漏极（14）彼此接触。 在包括接触孔（19）和（20）的内部的绝缘氧化膜上形成第一铝层的布线层。 布线层包括用于连接相邻存储单元晶体管的布线层（21A）和用于使源极（13）和漏极（14）短路的布线层（21B），以与耗尽相同的方式操作存储单元晶体管 型晶体管。

    Semiconductor memory with metallic interconnection layer of the same potential as the word line and connected thereto outside of the memory cell region
    4.
    发明公开
    Semiconductor memory with metallic interconnection layer of the same potential as the word line and connected thereto outside of the memory cell region 失效
    半导体存储器与由相同的电位的字线和与该存储区域外部连接的金属接合层。

    公开(公告)号：EP0421168A2

    公开(公告)日：1991-04-10

    申请号：EP90117656.0

    申请日：1990-09-13

    申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

    发明人： Takase, Shinsuke, c/o Intellectual Property Div. ,  Hashimoto, Hisashi, c/o Intellectual Property Div. ,  Tanaka, Yutaka, c/o Intellectual Property Div.

    IPC分类号： H01L27/118 ,  G11C8/00 ,  G11C5/06 ,  H01L27/112

    CPC分类号： H01L27/112 ,  H01L27/11803 ,  Y10S257/903

    摘要： Memory cells (21), which serve as basic cells, are arranged in a matrix pattern. The memory cells (21) are each provided with a word line (W′) which is integral with the gate electrode of a switch element (SW) and which is formed of polysilicon. A metallic interconnec­tion layer (M) is arranged above the word line (W′) and is applied with substantially the same potential as the word line (W′). The metallic interconnection layer (M) and the word line (W′) are connected together via through-holes (23A). The through-holes (23A) are formed in through-hole cells (23), which also serve as basic cells. The through-hole cells (23) and the memory cells (21) are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two.

    摘要翻译： 存储器单元（21），其用作基本单元，被布置成矩阵图案。 存储器单元（21）均设置有一个字线（W分钟），所有这些是与开关元件（SW）的栅极电极和积分的所有其上形成多晶硅构成。 的金属互连层（M）的字线（W分钟）以上被布置和被施加有基本上相同的电位作为字线（W分钟）。 该金属互连层（M）和字线（W分钟）经由通孔（23A）连接在一起。 通孔（23A）形成在贯通孔的细胞（23），其因此用作基本单元。 贯通孔的细胞（23）和存储单元（21）被布置检查做的前者和后者的行数的行数是在一个的至少两个的比率。