发明公开
- 专利标题: Compounding preprocessor for cache
- 专利标题(中): 用于缓存的组合预处理程序
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申请号: EP91104318.0申请日: 1991-03-20
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公开(公告)号: EP0455966A3公开(公告)日: 1993-11-10
- 发明人: Blaner, Bartholomew , Vassiliadis, Stamatis
- 申请人: International Business Machines Corporation
- 申请人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: Old Orchard Road Armonk, N.Y. 10504 US
- 代理机构: Schäfer, Wolfgang, Dipl.-Ing.
- 优先权: US522291 19900510
- 主分类号: G06F9/38
- IPC分类号: G06F9/38
摘要:
A digital computer system is described capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
公开/授权文献
- EP0455966B1 Compounding preprocessor for cache 公开/授权日:1995-12-13
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