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公开(公告)号：EP0496928B1
公开(公告)日：2000-02-02
申请号：EP91105248.8
申请日：1991-04-03
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017 , G06F9/3808 , G06F9/3812 , G06F9/3842 , G06F9/3853 , G06F9/3885
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2.发明公开System for preparing instructions for instruction parallel processor and system with mechanism for branching in the middle of a compound instruction 失效设备以制备用于与具有一个进程的化合物指令的中间分支并行命令和装置中的处理器的指令
公开(公告)号：EP0825529A3
公开(公告)日：1998-04-29
申请号：EP97119948.4
申请日：1991-03-29
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3853 , G06F9/3885
摘要： An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch, which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.
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3.发明公开System for preparing instructions for instruction parallel processor and system with mechanism for branching in the middle of a compound instruction 失效设备以制备用于与具有一个进程的化合物指令的中间分支并行命令和装置中的处理器的指令
公开(公告)号：EP0825529A2
公开(公告)日：1998-02-25
申请号：EP97119948.4
申请日：1991-03-29
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3853 , G06F9/3885
摘要： An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch, which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.
摘要翻译： 用于解码从一系列的标量机的基本指令创建化合物指令的指令处理器系统中，处理器生成与上指令的一系列化合物指令formatText具有在指令格式文本追加控制位使化合物指令格式的执行 与配制设施哪个取指和所述指令处理器的文本进行解码从而可以同时保留完好的标量机，其分别的基本指令的标量执行来执行的如由指令处理器的该算术和逻辑单元进行配料，并单指令化合物指令 最初在存储。 该系统勾销时的可能的条件下，：诸如分支发生的化合物指令中的一员指令单元的任何执行，这会影响部件的指令单元的执行的记录结果的正确性在基于化合物的成员单位的相互关系的部分 指令与其他指令。 得到的一系列复合指令基因的反弹比原来的格式更快地执行所有这一切都被保留，由于复合指令流的并行特性所有这一切都被执行。
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公开(公告)号：EP0726532A3
公开(公告)日：1997-03-19
申请号：EP96480018.9
申请日：1996-02-06
CPC分类号： G06F15/17381
摘要： A plurality of processor elements (PEs) are connected in a cluster by a common instruction bus to an instruction memory. Each PE has data buses connected to at least its four nearest PE neighbors, referred to as its North, South, East and West PE neighbors. Each PE also has a general purpose register file containing several operand registers. A common instruction is broadcast from the instruction memory over the instruction bus to each PE in the cluster. The instruction includes an opcode value that controls the arithmetic or logical operation performed by an execution unit in the PE on an operand from one of the operand registers in the register file. A switch is included in each PE to interconnect it with a first PE neighbor as the destination to which the result from the execution unit is sent. The broadcast instruction includes a destination field that controls the switch in the PE, to dynamically select the destination neighbor PE to which the result is sent. Further, the broadcast instruction includes a target field that controls the switch in the PE, to dynamically select the operand register in the register file of the PE, to which another result received from another neighbor PE in the cluster is stored. In this manner, the instruction broadcast to all the PEs in the cluster, dynamically controls the communication of operands and results between the PEs in the cluster, in a single instruction, multiple data processor array.
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公开(公告)号：EP0564847A3
公开(公告)日：1994-07-20
申请号：EP93104154.5
申请日：1993-03-15
IPC分类号： G06F15/80
CPC分类号： G06F15/8023
摘要： Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N x N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. Assuming a single wire interface between PEs, there are a total of 2N² wires in the mesh structure. Under the assumtion of SIMD operation with uni-directional message and data transfers between the processing elements in the meah, for example all PES transferring data North, it is possible to reconfigure the array by placing the symmetric processing elements together and sharing the north-south wires with the east-west wires, thereby reducing the wiring complexity in half, i.e. N² without affecting performance. The resulting diagonal folded mesh array processor, which is called Oracle, allows the matrix transformation operation to be accomplished in one cycle by simple interchange of the data elements in the dual symmetric processor elements. The use of Oracle for a parallel 2-D convolution mechanish for image processing and multimedia applications and for a finite difference method of solving differential equations is presented, concentrating on the computational aspects of the algorithm.
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7.发明公开An in-memory preprocessor for a scalable compound instruction set machine processor 失效用于可扩展复合指令集机器处理器的内存预处理器
公开(公告)号：EP0463296A3
公开(公告)日：1994-03-23
申请号：EP91104324.8
申请日：1991-03-20
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/3853 , G06F9/3885
摘要： A digital computer system is described capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译： 描述了能够并行处理两个或更多个计算机指令并且具有用于存储包括计算机指令的信息块的主存储器单元的数字计算机系统，包括指令复合单元，用于分析指令并向每个指令添加标记字段，该标记字段指示是 或者不是该指令可以与另一个相邻指令并行处理。 标记的说明存储在主存储器中。 计算机系统还包括彼此并行操作的多个功能指令处理单元。 提供给功能单元的指令是通过缓存存储单元从存储器获得的。 在指令发布时间，检查指令的标签字段，并将标签用于并行处理的标签字段根据其操作代码字段的编码发送到不同的功能单元。
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公开(公告)号：EP0499705A3
公开(公告)日：1993-03-10
申请号：EP91121058.1
申请日：1991-12-09
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F2207/5355
摘要： A system for dividing a digital dividend operand N by a digital divisor operand D to obtain a quotient operand Q with minimal execution time and hardware calculates a value NP₀P₁...P m , where the value P₀P₁...P m has a magnitude such that NP₀P₁...P m converges to Q and DP₀P₁ converges to 1. The divider employs a one's complementation, multiplication and addition sequence to calculate the value NP₀P₁...P m .
摘要翻译： 用数字除数操作数D将数字除数操作数N除以以最小执行时间和硬件获得商操作数Q的系统计算值NP0P1 ... Pm，其中值P0P1 ... Pm具有使得NP0P1 ... Pm收敛到Q，DP0P1收敛到1.分频器采用一个补码，乘法和相加序列来计算值NP0P1 ... Pm。
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9.发明公开An in-memory preprocessor for a scalable compound instruction set machine processor 失效In-Speicher-Vorverarbeitungseinrichtungfüreinen Prozessor mit skalarem Verbundbefehlssatz。
公开(公告)号：EP0463296A2
公开(公告)日：1992-01-02
申请号：EP91104324.8
申请日：1991-03-20
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/3853 , G06F9/3885
摘要： A digital computer system is described capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译： 描述了能够并行处理两个或更多个计算机指令的数字计算机系统，并且具有用于存储包括计算机指令的信息块的主存储单元，包括用于分析指令的指令复合单元，并向每个指令添加指示是否 或者不是该指令可以与另一个相邻指令并行处理。 标记的指令存储在主存储器中。 计算机系统还包括彼此并行操作的多个功能指令处理单元。 提供给功能单元的指令通过高速缓存存储单元从存储器获得。 在指令发布时，检查指令的标签字段，并根据其操作码字段的编码将用于并行处理的标签字段发送到不同的功能单元。
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公开(公告)号：EP0339296A3
公开(公告)日：1991-06-26
申请号：EP89105758.0
申请日：1989-04-01
IPC分类号： G06F11/10
摘要： Parity for every byte of the sum produced by addition of two operands is predicted based upon segmentation of each sum byte into three groups of adjacent bits, which leads to Boolean minterm circuitry employing a minimum of exclusive-OR gates.
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