发明公开
EP0457270A3 Floating diffusion type charge detection circuit for use in charge transfer device
失效
用于充电传输装置的浮动扩散型充电检测电路
- 专利标题: Floating diffusion type charge detection circuit for use in charge transfer device
- 专利标题(中): 用于充电传输装置的浮动扩散型充电检测电路
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申请号: EP91107783.2申请日: 1991-05-14
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公开(公告)号: EP0457270A3公开(公告)日: 1992-01-08
- 发明人: Miwada, Kazuo, c/o NEC Corporation
- 申请人: NEC CORPORATION
- 申请人地址: 7-1, Shiba 5-chome Minato-ku Tokyo JP
- 专利权人: NEC CORPORATION
- 当前专利权人: NEC CORPORATION
- 当前专利权人地址: 7-1, Shiba 5-chome Minato-ku Tokyo JP
- 代理机构: Glawe, Delfs, Moll & Partner
- 优先权: JP123692/90 19900514
- 主分类号: G11C27/04
- IPC分类号: G11C27/04 ; G11C19/28
摘要:
A floating diffusion type signal charge detection circuit for use in a charge transfer device includes a charge transfer region formed in a semiconductor layer, a plurality of transfer electrodes formed on the charge transfer region through an insulating layer, a floating diffusion formed in the semiconductor layer adjacent to a final stage of the charge transfer region, a reset drain formed in the semiconductor layer separate from the floating diffusion and connected to a reset drain voltage, and a reset gate formed through an insulating layer on a portion of the semiconductor layer between the floating diffusion and the reset drain. The floating diffusion, the reset drain and the reset gate forms a reset transistor. An amplifier is connected at its input to the floating diffusion so as to detect a voltage change appearing in the floating diffusion. The amplifier includes a first amplification stage having a first MOS transistor having a gate connected to the floating diffusion and a drain connected to a high voltage, a source of the first MOS transistor being connected to a first load so that a first source follower is formed, and a second amplification stage having an input connected to the source of the first MOS transistor and an output node connected to an output terminal. An output control circuit is connected to the first MOS transistor and controlled in synchronism with a reset pulse applied to the reset gate so that when the reset transistor is off, the first source follower outputs an signal having a level higher than that outputted from the first source follower when the reset transistor were on.
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