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    FAST READOUT METHOD AND SWITCHED CAPACITOR ARRAY CIRCUITRY FOR WAVEFORM DIGITIZING
    1.
    发明授权
    FAST READOUT METHOD AND SWITCHED CAPACITOR ARRAY CIRCUITRY FOR WAVEFORM DIGITIZING 有权

    公开(公告)号：EP2198429B1

    公开(公告)日：2018-10-31

    申请号：EP08801788.4

    申请日：2008-09-02

    申请人： Paul Scherrer Institut PSI

    发明人： RITT, Stefan ,  DINAPOLI, Roberto

    IPC分类号： G11C27/02 ,  G11C27/04 ,  G11C19/18 ,  G06G7/26

    CPC分类号： G11C27/024 ,  G06G7/26 ,  G11C19/188 ,  G11C27/04

    摘要： The present invention represents a technique to reduce the readout time of switched capacitor array (SCA) circuitries. A possible implementation is a SCA chip capable of sampling 12 differential input channels at a sampling speed of 10 MSPS to 5 GSPS. The analog waveform can be stored in 1024 sampling cells per channel, and can be read out after sampling via a shift register clocked at 33 MHz for external digitization. The write signal for the sampling cells is generated by a chain of inverters (domino principle) generated on the chip. The domino wave is running continuously until stopped by a trigger. A read shift register clocks the contents of the sampling cells either to a multiplexed or to individual outputs, where it can be digitized with an external ADC. It is possible to read out only a part of the waveform for reducing the digitization time. The high channel density, high analog bandwidth of 450 MHz, and low noise of 0.35 mV (after offset calibration) makes this chip ideally suited for low power, high speed, high precision waveform digitizing. Fabricated on an advanced CMOS process in a radiation hard design, the present chip is available in a 64-lead low profile quad flat pack (LQFP) and a 64-pin quad flat non-leaded package (QFN).

    FAST READOUT METHOD AND SWITCHED CAPACITOR ARRAY CIRCUITRY FOR WAVEFORM DIGITIZING
    2.
    发明公开
    FAST READOUT METHOD AND SWITCHED CAPACITOR ARRAY CIRCUITRY FOR WAVEFORM DIGITIZING 审中-公开
    SCHNELLES AUSLESUNGSVERFAHREN UND SCHALTKONDENSATOR-ARRAYSCHALTUNG ZUR WELLENFORM-DIGITALISIERUNG

    公开(公告)号：EP2198429A1

    公开(公告)日：2010-06-23

    申请号：EP08801788.4

    申请日：2008-09-02

    申请人： Paul Scherrer Institut PSI

    发明人： RITT, Stefan ,  DINAPOLI, Roberto

    IPC分类号： G11C27/02 ,  G11C27/04

    CPC分类号： G11C27/024 ,  G06G7/26 ,  G11C19/188 ,  G11C27/04

    摘要： The present invention represents a technique to reduce the readout time of switched capacitor array (SCA) circuitries. A possible implementation is a SCA chip capable of sampling 12 differential input channels at a sampling speed of 10 MSPS to 5 GSPS. The analog waveform can be stored in 1024 sampling cells per channel, and can be read out after sampling via a shift register clocked at 33 MHz for external digitization. The write signal for the sampling cells is generated by a chain of inverters (domino principle) generated on the chip. The domino wave is running continuously until stopped by a trigger. A read shift register clocks the contents of the sampling cells either to a multiplexed or to individual outputs, where it can be digitized with an external ADC. It is possible to read out only a part of the waveform for reducing the digitization time. The high channel density, high analog bandwidth of 450 MHz, and low noise of 0.35 mV (after offset calibration) makes this chip ideally suited for low power, high speed, high precision waveform digitizing. Fabricated on an advanced CMOS process in a radiation hard design, the present chip is available in a 64-lead low profile quad flat pack (LQFP) and a 64-pin quad flat non-leaded package (QFN).

    摘要翻译： 本发明表示减少开关电容器阵列（SCA）电路的读出时间的技术。 可能的实现是SCA芯片能够以10 MSPS至5 GSPS的采样速度对12个差分输入通道进行采样。 模拟波形可以存储在每个通道的1024个采样单元中，并且可以通过33 MHz时钟的移位寄存器采样后进行外部数字化读出。 采样单元的写入信号由芯片上产生的反相器链（domino principle）产生。 多米诺骨牌一直持续运行，直到被触发器停止。 读取移位寄存器将采样单元的内容或多路复用或单独输出进行计时，其中可以使用外部ADC进行数字化。 只能读出波形的一部分以减少数字化时间。 高通道密度，450 MHz高模拟带宽和0.35 mV的低噪声（偏移校准后）使该芯片非常适合低功耗，高速度，高精度波形数字化。 该芯片采用先进的CMOS工艺制造，采用辐射硬设计，采用64引脚低成形四边形扁平封装（LQFP）和64引脚四边形扁平非引线封装（QFN）。

    Analog fifo memory device
    5.
    发明公开
    Analog fifo memory device 失效
    模拟fifo存储设备

    公开(公告)号：EP0878770A3

    公开(公告)日：2002-01-02

    申请号：EP98108812.3

    申请日：1998-05-14

    申请人： Matsushita Electric Industrial Co., Ltd.

    发明人： Dosho, Shiro ,  Yanagisawa, Naoshi

    IPC分类号： G06J1/00 ,  G11C27/04

    CPC分类号： G06J1/00

    摘要： An analog FIFO memory device allowing for the suppression of the adverse effects produced by fixed pattern noise, generated inside an analog FIFO memory, on signal components. First and second analog multipliers are respectively provided on the input and output sides of the analog FIFO memory. In synchronism with the inputs/outputs of signals to/from the analog FIFO memory, a non-inverting operation and an inverting operation are alternately and repeatedly performed on the input signals and the output signals. Then, although the signal input/output characteristics of the analog FIFO memory are not changed, the fixed pattern noise generated inside the analog FIFO memory is modulated by the second analog multiplier. As a result, the spectrum of the fixed pattern noise, which originally has a lower frequency, is shifted to have a higher frequency. That is to say, since a signal band can be separated from the fixed pattern noise in terms of frequency, the fixed pattern noise can be eliminated by a low pass filter. Consequently, even when the analog FIFO memory device of the present invention is applied for delaying TV signals, the resulting TV image quality is not deteriorated.

    摘要翻译： 一种模拟FIFO存储器件，可以抑制由模拟FIFO存储器内部产生的固定模式噪声对信号分量产生的不利影响。 第一和第二模拟乘法器分别设置在模拟FIFO存储器的输入和输出侧。 与来自/来自模拟FIFO存储器的信号的输入/输出同步，对输入信号和输出信号交替地和重复地执行非反相操作和反相操作。 然后，尽管模拟FIFO存储器的信号输入/输出特性没有改变，但模拟FIFO存储器内产生的固定模式噪声由第二个模拟乘法器调制。 结果，原本具有较低频率的固定模式噪声的频谱被移位以具有较高的频率。 也就是说，由于信号频带在频率方面可以与固定模式噪声分离，固定模式噪声可以通过低通滤波器消除。 因此，即使在应用本发明的模拟FIFO存储装置来延迟电视信号时，所得到的电视图像质量也不会恶化。

    Switching circuit and charge transfer device using same
    7.
    发明公开
    Switching circuit and charge transfer device using same 失效
    使用相同的开关电路和电荷耦合器件

    公开(公告)号：EP0734026A3

    公开(公告)日：1999-03-17

    申请号：EP96104156.3

    申请日：1996-03-15

    申请人： SONY CORPORATION

    发明人： Maki, Yasuhito, c/o Sony Corporation

    IPC分类号： G11C27/04

    CPC分类号： G11C27/04

    摘要： A switching circuit comprising a means for holding a signal or a DC component thereof, and a switching transistor for driving the holding means, wherein another means is included for shaping the trailing edge to be more obtuse in the fall of a driving pulse applied to a gate of the switching transistor. There is also disclosed a charge transfer device comprising a charge transferrer for transferring a signal charge, a charge-voltage converter for converting the transferred signal charge into a proportional voltage, and a driver for supplying a reset pulse to the charge-voltage converter so as to reset the capacitance thereof to a predetermined potential, wherein another a means is incorporated in the driver for shaping the trailing edge to be more obtuse in the fall of the reset pulse. Since the trailing edge of the reset pulse at the time of turning off the reset is rendered more obtuse, it becomes possible to reduce the coupling portion of the output waveform where the potential of a floating diffusion or a floating gate is varied by the capacitive coupling which is derived from the parasitic capacitance between a reset drain and a reset gate.

    Verzögerungsschaltung
    8.
    发明公开
    Verzögerungsschaltung 失效
    延迟电路

    公开(公告)号：EP0725404A3

    公开(公告)日：1998-10-07

    申请号：EP96200159

    申请日：1996-01-23

    申请人： PHILIPS PATENTVERWALTUNG ,  PHILIPS ELECTRONICS NV

    发明人： STRUCK SOENKE

    IPC分类号： G11C27/04 ,  H03H11/26

    CPC分类号： G11C27/04

    摘要： Die Erfindung bezieht sich auf eine Verzögerungsschaltung mit wenigstens zwei Speicherzellen (3,4,5,6,8,9), welche je ein kapazitives Speicherelement (20,26,40,45), einen Schreibtransistor (22,28,42,47), mittels dessen eine zu verzögernde Information aus einer Schreibleitung (18) in das kapazitive Speicherelement (20,26,40,45) einschreibbar ist, und einen Lesetransistor (21,27,41,46) aufweisen, mittels dessen eine Information aus dem kapazitiven Speicherelement (20,26,40,45) auf eine Leseleitung (19) auslesbar ist, und mit einer mittels eines ersten Steuertaktes getakteten Steueranordnung, welcher eingangsseitig ein Steuersignal zugeführt wird und welche miteinander gekoppelte Steuerschaltungen (11,12,13,14,15,16) aufweist, von denen jeweils eine je einer Speicherzelle (3,4,5,6,8,9) zugeordnet ist, wobei mittels des Eingangssignals jeder Steuerschaltung (11,12,13,14,15,16) der Lesetransistor (21,27,41,46) der zugeordneten Speicherzelle (3,4,5,6,8,9) und mittels des Ausgangssignals jeder Steuerschaltung (11,12,13,14,15,16) der Schreibtransistor (22,28,42,47) der zugeordneten Speicherzelle ansteuerbar ist, wobei jede Steuerschaltung (11,12,13,14,15,16) ein erstes (43,48,24,30) und ein diesem nachgeschaltetes zweites (44,49,25,31) Steuerelement aufweist, diejenigen Steuerschaltungen (14) ein drittes, dem ersten Steuerelement (30) vorgeschaltetes Steuerelement (29) aufweisen, deren vorgeschaltete Steuerschaltung (11) örtlich entfernt angeordnet ist, daß den dritten Steuerelementen (29) eingangsseitig das Ausgangssignal des ersten Steuerelementes (24) der jeweils vorgeschalteten, räumlich entfernt angeordneten Steuerschaltung (11) zugeführt wird, und daß die ersten Steuerelemente (43,48,24,30) der Steuerschaltungen (11,12,13,14,15,16) von dem ersten Takt und die zweiten (44,49,25,31) und dritten (29) Steuerelemente der Steuerschaltungen (11,12,13,14,15,16) von einem zweiten Takt getaktet werden.