发明公开
EP0457591A3 Semiconductor memory device having reduced parasitic capacities between bit lines
失效
具有位线之间降低的PARASIIC能力的半导体存储器件
- 专利标题： Semiconductor memory device having reduced parasitic capacities between bit lines
- 专利标题（中）： 具有位线之间降低的PARASIIC能力的半导体存储器件
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申请号： EP91304409.5申请日： 1991-05-16
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公开(公告)号： EP0457591A3公开(公告)日： 1992-10-21
- 发明人: Taguchi, Masao
- 申请人： FUJITSU LIMITED
- 申请人地址： 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 JP
- 专利权人： FUJITSU LIMITED
- 当前专利权人： FUJITSU LIMITED
- 当前专利权人地址： 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 JP
- 代理机构： Skone James, Robert Edmund
- 优先权： JP127524/90 19900517
- 主分类号： G11C7/00
- IPC分类号： G11C7/00 ; G11C11/409
摘要：
In a semiconductor memory device having a memory cell array (MCA) and sense amplifiers (SA₁, SA₂, ...) connected by bit lines (BL₁, BL ₂, ...), a conductive shield plate (SLD) is arranged over the bit lines and between memory cell array and the sense amplifiers.
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