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    On-chip voltage regulator and semiconductor memory device using the same
    7.
    发明公开
    On-chip voltage regulator and semiconductor memory device using the same 失效
    On-Chip-Spannungsregler und Halbleiterspeichervorrichtung mit Verwendung desgleichen。

    公开(公告)号：EP0449310A2

    公开(公告)日：1991-10-02

    申请号：EP91105071.4

    申请日：1991-03-28

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao

    IPC分类号： G05F1/46 ,  G11C5/14

    CPC分类号： G11C5/147 ,  G05F1/465

    摘要： An on-chip voltage regulator controls a gate of a regulator transistor (Q1) having a first terminal connectable to receive an external power supply voltage (V EXT ) and a second terminal connectable to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The regulator includes a clock receiving part (Q30) for receiving a predetermined clock signal related to an operation of the internal circuit, and a regulator part (i, Q26 - Q31) for generating a gate voltage (V G1 ) output to the gate of the regulator transistor on the basis of a state of the predetermined clock signal so that the regulator transistor can generate a substantially fixed internal voltage (V INT ) from the external power supply voltage irrespective of whether or not the internal circuit is operating.

    摘要翻译： 片上稳压器控制具有可连接以接收外部电源电压（VEXT）的第一端子的稳压晶体管（Q1）的栅极和可连接到芯片上形成的内部电路的第二端子，片上 形成稳压器。 调节器包括用于接收与内部电路的操作相关的预定时钟信号的时钟接收部分（Q30），以及用于产生输出到所述内部电路的门的栅极电压（VG1）的调节器部分（i，Q26-Q31） 基于预定时钟信号的状态调节晶体管，使得调节器晶体管可以从外部电源电压产生基本上固定的内部电压（VINT），而不管内部电路是否工作。

    Mask, mask producing method and pattern forming method using mask
    8.
    发明公开
    Mask, mask producing method and pattern forming method using mask 失效
    Maske，Herstellungsverfahren und Musterherstellung mit einer solchen Maske。

    公开(公告)号：EP0395425A2

    公开(公告)日：1990-10-31

    申请号：EP90304571.4

    申请日：1990-04-26

    申请人： FUJITSU LIMITED

    发明人： Kawabata, Toshiaki ,  Nakagawa, Kenji ,  Yamaguchi, Seiichiro ,  Taguchi, Masao ,  Sumi, Kazuhiko ,  Yanagishita, Yuichiro

    IPC分类号： G03F1/14

    CPC分类号： G03F1/29 ,  G03F1/28 ,  G03F1/30 ,  G03F1/34

    摘要： A mask includes a transparent layer (2) which is transparent with respect to a light which is used for an exposure, and a mask pattern layer (5) which is formed on the transparent layer. At least a portion of the mask pattern layer (5) is made up solely of a phase shift layer (3a) for transmitting the light, so that a phase shift occurs between a phase of the light transmitted through the phase shift layer and a phase of the light transmitted through a portion of the mask having no phase shift layer.

    摘要翻译： 掩模包括相对于用于曝光的光透明的透明层（2）和形成在透明层上的掩模图案层（5）。 掩模图案层（5）的至少一部分仅由用于透射光的相移层（3a）构成，使得在透过相移层的光的相位和相位 的透射通过没有相移层的掩模的一部分。

    Semiconductor memory device
    9.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0234891A3

    公开(公告)日：1987-11-25

    申请号：EP87301506

    申请日：1987-02-20

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao

    IPC分类号： H01L27/10

    CPC分类号： H01L27/10829

    摘要： A semiconductor memory device comprises a semiconductor substrate (1) of one conductivity type (p); a transistor (Tr) formed on the said substrate (1) and having a portion (92) serving as a source or drain, which portion is of the opposite conductivity type (n); and a storage capacitor (SC), comprising a first relatively conductive member consisting of a layer (5) provided on an inner surface region of a recess (4), formed in the said substrate (1), a dielectric layer (6) covering the said first conductive member (5) in the recess, and a second relatively conductive member (7) filling a remaining portion of the recess (4), so as to be surrounded by the said dielectric layer (6); there being an electrical connection between the said second conductive member (7) and the said portion (92) of the transistor (Tr). Such a memory device can reduce the occurrence of punch-through between adjacent storage (trench) capacitors and can reduce the possibility of soft errors.

    摘要翻译： 一种半导体存储器件包括一种导电类型（p）的半导体衬底（1）; 形成在所述衬底上并具有用作源极或漏极的部分的导电类型相反的晶体管Tr; 和存储电容器（SC），包括：第一相对导电部件，形成在所述衬底（1）中的由设置在凹槽（4）的内表面区域上的层（5）构成;电介质层（6），覆盖 所述凹部中的所述第一导电构件以及填充所述凹部的剩余部分的第二相对导电构件以被所述电介质层包围。 在所述第二导电部件（7）和晶体管（Tr）的所述部分（92）之间存在电连接。 这种存储器件可以减少相邻存储（沟槽）电容器之间穿通的发生并且可以减少软错误的可能性。