A circuit for compressing and expanding video data comprises a FIFO line memory (356) and an interpolator (337). A timing circuit (339) generates control signals for writing data into the line memory (356) and for reading data from the line memory (356) to compress and expand the data. The interpolator (337) smooths the data compressed or expanded in the FIFO line memory (356). A switching network (325, 327, 353) selectively establishes a first signal path in which the line memory (356) precedes the interpolator (337) for implementing the data expansion and a second signal path in which the interpolator (337) precedes the line memory (356) for implementing the data compression. The switching network (325, 327, 333) is controlled according to selected display formats requiring compression or expansion, for example by a microprocessor.