A dc-coupled packet mode digital data receiver for use with an optical bus, uses a peak detector(s) A 2P , A 2N to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A reset circuit (620) resets the peak detector(s) and other circuits of the receiver in response to an end-of-packet reset signal, thereby enabling the reception of closely-spaced burst date packets which have greatly differing power levels.