摘要:
A digital burst-mode packet data receiver receives (by PD1) high-speed burst-mode packet data signals superimposed on a lower frequency data signal. The receiver includes a first detector (PEAK DETECTOR) for detecting the received high-speed burst-mode packet data which is reset (by RESET) during the time period between consecutive bursts of the high-speed packet data signal. A second detector (SHI) detects the lower frequency data signal during a predetermined portion of the time period between consecutive bursts of the high-speed packet data.
摘要:
A dc-coupled packet mode digital data receiver for use with an optical bus, uses a peak detector(s) A 2P , A 2N to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A reset circuit (620) resets the peak detector(s) and other circuits of the receiver in response to an end-of-packet reset signal, thereby enabling the reception of closely-spaced burst date packets which have greatly differing power levels.
摘要:
A burst mode digital data receiver automatically adjusts its logic reference voltage to be equal to one-half of the sum of the minimum and maximum excursions of a received data signal. The receiver includes a differential amplifier circuit which has a first input for receiving the data signal and a second input connected to a voltage reference circuit. The voltage reference circuit is responsive to an output signal from the amplifier circuit to produce the required logic reference voltage at the second input to the amplifier circuit by generating a feedback signal which causes the amplifier circuit to have a first gain value during the absence of the data signal and while the data signal is less than its peak amplitude and a second gain value approximately twice the first gain value for a predetermined time after the peak amplitude of the data signal is reached.
摘要:
A dc-coupled packet mode digital data receiver, for use with an optical bus uses peak detectors ( A 2P , A 2N ) to adaptively establish an instantaneous logic threshold at the beginning of a data burst. A dc compensator ( I COMP ), responsive to outputs of the peak detectors, shunts dc or low frequency currents, corresponding to "dark level" optical signals, from the input of the receiver.
摘要:
A burst mode digital data receiver automatically adjusts its logic reference voltage to be equal to one-half of the sum of the minimum and maximum excursions of a received data signal. The receiver includes a differential amplifier circuit which has a first input for receiving the data signal and a second input connected to a voltage reference circuit. The voltage reference circuit is responsive to an output signal from the amplifier circuit to produce the required logic reference voltage at the second input to the amplifier circuit by generating a feedback signal which causes the amplifier circuit to have a first gain value during the absence of the data signal and while the data signal is less than its peak amplitude and a second gain value approximately twice the first gain value for a predetermined time after the peak amplitude of the data signal is reached.