A method of semiconductor integrated circuit fabrication including a technique for forming punch-through control implants (e.g., 37, 39) is disclosed. After gate (e.g., 13, 15) formation, a dielectric (e.g., 17) is formed which covers the gate (e.g., 13, 15) and exposed portions of a semiconductor substrate (e.g., 11). The dielectric is formed by a process which makes that portion of the dielectric adjacent the gate sidewalls more vulnerable to wet etching than those portions of the dielectric which are adjacent the top of the gate and the exposed substrate. The dielectric is then subsequently etched to form channels (e.g., 29, 31) adjacent the gate which exposed the substrate and served to collimate an ion (e.g., 35) implantation beam. The remaining portions of the dielectric may then be stripped away and conventional procedures employed to form source (e.g., 45) and drain (e.g., 47). Illustratively, the dielectric is formed from TEOS to which NF 3 is added during the deposition process. The addition of NF 3 makes that portion of the dielectric which forms adjacent the gate sidewalls particularly vulnerable to hydrofluoric acid etching while those portions of the dielectric covering the substrate and covering the gate (e.g., 13, 15) are not so vulnerable.