公开(公告)号：EP0716442A1

公开(公告)日：1996-06-12

申请号：EP95308768.1

申请日：1995-12-05

Applicant: AT&T Corp.

Inventor： Lee, Kuo-Hua ,  Yu, Chen-Hua Douglas

IPC: H01L21/76

CPC classification number: H01L21/76264 ,  H01L21/76227 ,  H01L21/76281

Abstract: A method of field oxide formation which creates field oxides of comparatively uniform height between differently-spaced oxidation masks is disclosed. A patterned oxidation mask, typically silicon nitride (25, 23, 21), (possibly with underlying polysilicon) is formed. A blanket layer of polysilicon 141 is formed and etched back, thereby filling spaces between closely-spaced portions of the oxidation mask and fillets between less-closely spaced portions. A thermal oxidation is performed to produce a field oxide 155, 157. The field oxide has comparatively uniform height despite differences in oxidation mask spacing.

Abstract translation: 公开了一种在不同间隔的氧化掩模之间产生具有相对均匀高度的场氧化物的场氧化物形成方法。 形成图案化的氧化掩模，通常形成氮化硅（25,23,21）（可能具有下面的多晶硅）。 形成并覆盖多晶硅141的覆盖层，从而填充氧化掩模的紧密间隔的部分和较不紧密间隔的部分之间的圆角之间的空间。 进行热氧化以产生场氧化物155,157。尽管氧化掩模间隔有差异，场氧化物具有相对均匀的高度。

公开(公告)号：EP0643417A2

公开(公告)日：1995-03-15

申请号：EP94306395.8

申请日：1994-08-31

Applicant: AT&T Corp.

Inventor： Lee, Kuo-Hua ,  Yu, Chen-Hua Douglas

IPC: H01L21/3215 ,  H01L21/336 ,  H01L21/265 ,  H01L21/28

CPC classification number: H01L21/28035 ,  H01L21/32155

Abstract: A method for forming silicon integrated circuits is disclosed. Ion implantation of polysilicon gates is accomplished by directing a dopant species (21) at a polysilicon layer (19) at an angle instead of normal incidence. The angularly directed dopant species cannot channel through the polysilicon layer and, furthermore, the dopant species "sees" a thicker effective polysilicon layer (19).

Abstract translation: 公开了一种用于形成硅集成电路的方法。 多晶硅栅极的离子注入是通过以一个角度而不是垂直入射来引导多晶硅层（19）处的掺杂剂物质（21）来实现的。 有角度的掺杂剂物质不能通过多晶硅层，此外，掺杂物质“看到”更厚的有效多晶硅层（19）。

公开(公告)号：EP0550171A3

公开(公告)日：1993-09-08

申请号：EP92311249.4

申请日：1992-12-10

Applicant: AT&T Corp.

Inventor： Lee, Kuo-Hua ,  Yu, Chen-Hua Douglas

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76838 ,  H01L21/32155 ,  Y10S148/147

Abstract: A method is disclosed of making contacts to a metal silicide layer (5) in an integrated circuit. Normally polycrystalline silicon is used, but it is found that spikes are then formed. In the present invention a layer (11) of amorphous silicon (α=Si) is deposited at a temperature less than the recrystallization temperature (which is about 575°C) and then implanted with a dopant (e.g.P) having the peak of its special distribution within the layer, spaced from the interfaces. It was found that spikes were formed, and, when the deposition temperature was below about 550°C none at all were observed.

公开(公告)号：EP0550174A2

公开(公告)日：1993-07-07

申请号：EP92311252.8

申请日：1992-12-10

Applicant: AT&T Corp.

Inventor： Lee, Kuo-Hua ,  Yu, Chen-Hua Douglas

IPC: H01L21/60 ,  H01L21/336

CPC classification number: H01L21/76897 ,  H01L29/66575

Abstract: A self aligned contact to the substrate(e.g. 1) in the region between two gate electrodes(e.g. 3) is formed by depositing a conformal dielectric layer-(e.g. 13) and patterning to form a contact window-(e.g. 17). The conductive elements of the gate electrode(e.g. 3) are not contacted because of etch rate differentials between the conformal dielectric-(e.g. 13) and the insulating elements(e.g. 11) of the gate structure(e.g. 3).

Abstract translation: 在两个栅电极（例如3）之间的区域中与衬底（例如1）的自对准接触通过沉积保形电介质层（例如13）并构图以形成接触窗（例如17）而形成。 由于保形电介质（例如13）和栅极结构（例如3）的绝缘元件（例如11）之间的蚀刻速率差异，栅电极（例如3）的导电元件不接触。

公开(公告)号：EP0549168A2

公开(公告)日：1993-06-30

申请号：EP92311092.8

申请日：1992-12-04

Applicant: AT&T Corp.

Inventor： Lee, Kuo-Hua ,  Yu, Chen-Hua Douglas

IPC: H01L21/28 ,  H01L21/3215 ,  H01L21/82

CPC classification number: H01L21/28061 ,  H01L21/32155 ,  Y10S148/034

Abstract: A method of forming p⁺ transistor gates is disclosed. A polysilicon layer (e.g., 15) is covered with an amorphous silicide layer (e.g., 17) which prevents penetration of p type dopants through the gate oxide (e.g., 13). The silicide (e.g., 17) may be covered by a dielectric (e.g., 19) which is formed at a temperature low enough to prevent crystallization of the silicide.

Abstract translation: 公开了一种形成p + +晶体管栅极的方法。 多晶硅层（例如15）被无定形硅化物层（例如17）覆盖，其阻止p型掺杂剂穿过栅极氧化物（例如13）。 硅化物（例如17）可以被形成在足够低的温度下形成的电介质（例如19），以防止硅化物的结晶化。

公开(公告)号：EP0516334A3

公开(公告)日：1992-12-09

申请号：EP92304590.0

申请日：1992-05-20

Applicant: AT&T Corp.

Inventor： Lee, Kuo-Hua ,  Yu, Chen-Hua Douglas

IPC: H01L21/90 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/3105 ,  H01L21/76804

Abstract: A method of semiconductor integrated circuit fabrication which provides a tapered window and a smoothed dielectric. A trench (e.g., 45) is made by etching through patterned photoresist into a dielectric (e.g., 43). Then the corners (e.g., 49, 60) of the trench are smoothed by thermal flow. Next the trench (e.g., 45) is etched downward by RIE blanket etchback. A window with tapered sides is thereby opened to the substrate (e.g., 23) and the dielectric is simultaneously smoothed.

公开(公告)号：EP0455413A3

公开(公告)日：1992-09-16

申请号：EP91303713.1

申请日：1991-04-24

Applicant: AT&T Corp.

Inventor： Manocha, Ajit Singh ,  Yu, Chen-Hua Douglas

IPC: H01L21/90

CPC classification number: H01L21/76801 ,  H01L21/7688 ,  Y10S148/10 ,  Y10S438/951

Abstract: A planar surface is produced in integrated circuit processing by patterning a bilevel structure(13) of a conductor(5) and a sacrificial layer(7) followed by directional deposition of a dielectric(5) and lift off of the sacrificial layer(7). An additional dielectric layer(17) may now be deposited if desired.

公开(公告)号：EP0649166B1

公开(公告)日：2001-02-28

申请号：EP94307274.4

申请日：1994-10-05

Applicant: AT&T Corp.

Inventor： Lee, Kuo-Hua ,  Yu, Chen-Hua Douglas

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L21/28123 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

公开(公告)号：EP0716455B1

公开(公告)日：2000-03-01

申请号：EP95308754.1

申请日：1995-12-05

Applicant: AT&T Corp.

Inventor： Lee, Kuo-Hua ,  Yu, Chen-Hua Douglas

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L29/4925 ,  H01L21/28044 ,  H01L21/823842

公开(公告)号：EP0646957A1

公开(公告)日：1995-04-05

申请号：EP94306938.5

申请日：1994-09-21

Applicant: AT&T Corp.

Inventor： Yu, Chen-Hua Douglas

IPC: H01L21/8238 ,  H01L21/283 ,  H01L21/266

CPC classification number: H01L21/823835 ,  H01L21/28061 ,  H01L29/66545 ,  Y10S148/106 ,  Y10S148/147

Abstract: A workpiece is formed comprising a silicon substrate (12,14,16) covered by four successive layers of silicon dioxide, undoped polysilicon, undoped WSi₂ and a top layer of silicon dioxide on silicon nitride. The four layers are patterned to provide gate electrode structures (30,40) each comprising the four layers. The workpiece is covered with a masking layer (42) and the top layer (28a) of each structure is exposed through the masking layer. The top layers are then removed and ions of one conductivity type are implanted into the WSi₂ layers of one group of gate electrode structures while another group of structures is masked, and ions of the other conductivity type are implanted into the WSi₂ layers of the second group while the first group is masked. Thereafter, doped regions are formed in the substrate adjacent to the gate electrode structures.

Abstract translation: 的半导体器件制造公司。 方法包括：（a）形成一个第一介电层，第二未掺杂的硅层，然后在半导体基板上的第三无掺杂二硅化钨层; （B）选择性地图案化该层以形成间隔开的第一和第二结构，每个包括三个层和邻接基底的暴露的表面部分; （C）掺杂p型离子的第一结构，而第二结构的第三层是掩蔽的第三层; 和（d）中掺杂n型离子的第二结构的第三层，而第一结构的第三层被屏蔽。 步骤（c）执行通过涂覆的结构和与第一掩模层相邻的暴露的表面部分，图案化所述掩膜层以暴露这两种结构的第三层，覆盖这两种结构和具有第二掩蔽层邻接衬底的部分，图案化所述第二 掩蔽层以暴露所述第一结构和离子注入p型离子注入到所述第一结构的暴露第三层的第三层。 所以声称是一个类似的过程，其中因此结构具有材料可蚀刻选择性w.r.t.的第四层 第三层，在所述第一掩模层图案化操作被移除该第四层。