发明公开
EP0608667A1 Driving circuit for a field effect transistor in final semibridge stage
失效
Treiberschaltungfüreinen Feldeffekttistoristor在einerHalbbrückenausgangsstufe。
- 专利标题： Driving circuit for a field effect transistor in final semibridge stage
- 专利标题（中）： Treiberschaltungfüreinen Feldeffekttistoristor在einerHalbbrückenausgangsstufe。
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申请号： EP93830034.0申请日： 1993-01-29
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公开(公告)号： EP0608667A1公开(公告)日： 1994-08-03
- 发明人: Pulvirenti, Francesco , Gariboldi, Roberto
- 申请人： SGS-THOMSON MICROELECTRONICS S.r.l. , CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
- 申请人地址： Via C. Olivetti, 2 I-20041 Agrate Brianza (Milano) IT
- 专利权人： SGS-THOMSON MICROELECTRONICS S.r.l.,CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
- 当前专利权人： SGS-THOMSON MICROELECTRONICS S.r.l.,CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
- 当前专利权人地址： Via C. Olivetti, 2 I-20041 Agrate Brianza (Milano) IT
- 代理机构： Checcacci, Giorgio
- 主分类号： H03K17/687
- IPC分类号： H03K17/687
摘要：
A drive circuit for a field-effect transistor (MFET1) which has a drain terminal connected to the positive pole (+Vcc) of the power supply and a source terminal connected to a load (OUT).
The circuit has circuit means for turning off the field-effect transistor (MFET1) which comprises a first transistor (M1) connected between the gate terminal of the field-effect transistor (MFET1) and the negative pole (GND) of the power supply.
Said first transistor (MFET1) is driven by an operational amplifier (M3,M4,MR1,MR2,MR3) which has inverting and non-inverting terminals connected to the gate and source terminals of the field-effect transistor (MFET1) respectively.
The circuit has circuit means for turning off the field-effect transistor (MFET1) which comprises a first transistor (M1) connected between the gate terminal of the field-effect transistor (MFET1) and the negative pole (GND) of the power supply.
Said first transistor (MFET1) is driven by an operational amplifier (M3,M4,MR1,MR2,MR3) which has inverting and non-inverting terminals connected to the gate and source terminals of the field-effect transistor (MFET1) respectively.
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