发明公开
EP0609626A3 High performance cascadable simplex switch 失效
级联的高性能交换系统以单工方式。

High performance cascadable simplex switch
摘要:
A serial simplex switch 14 design is provided which includes I/O ports 20 each of which is configurable specifically for attachment to a data communications subsystem 12 or, alternatively, for cascaded connection to a similarly configured I/O port 20 on another switch 14. The switch 14 provides a packet routing function including input 32 and output 36 buffers for each of its I/O ports 20 wherein packets of control messages sent by one subsystem 20 are temporarily stored prior to being delivered to the appropriate destination subsystem 20. When configured to be directly attached to a subsystem 20, the I/O ports 20 separate control messages from incoming integrated data and control message strings. In a cascade configuration, however, a mechanism is provided wherein data and control messages are separated into two physical paths to eliminate the delays associated with integrated data and control message flow through the cascaded I/O port 20. Each I/O port 20 is configurable to either of these methods of operation by means of programmable latches associated with the I/O port 20.
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