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发明公开
EP0632385A1 Semiconductor integrated circuit including test circuit 失效
Integrierte Halbleiterschaltung mitPrüfschaltung。

Semiconductor integrated circuit including test circuit
摘要：
A first test circuit (21) is connected to one end of a first wiring line (40), and a second test circuit (22) is connected to one end of a second wiring line (41). The second wiring line (41) serves as a data bus. N-channel MOS transistors (50, 51), connected in series, are provided between the first and second wiring lines (40, 41) and located below a third wiring line (42). The transistors (50, 51) are set in an conductive state by a gate control signal (TEST) from a test control circuit (53) in a test mode, and are set in an OFF state in a normal operation mode. In the normal operation mode, the capacitance between the first and second wiring lines (40, 41) is small and does not adversely affect the operation speed of an integrated circuit.
摘要（中）：

第一测试电路（21）连接到第一布线（40）的一端，第二测试电路（22）连接到第二布线（41）的一端。 第二布线（41）用作数据总线。 串联连接的N沟道MOS晶体管（50,51）设置在第一和第二布线（40,41）之间并位于第三布线（42）的下方。 晶体管（50,51）在测试模式下通过来自测试控制电路（53）的门控制信号（TEST）设置在导通状态，并且在正常操作模式中被设置为OFF状态。 在正常工作模式中，第一和第二布线（40,41）之间的电容小，对集成电路的运行速度没有不利影响。

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