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1.发明公开Semiconductor integrated circuit including test circuit 失效Integrierte Halbleiterschaltung mitPrüfschaltung。
公开(公告)号：EP0632385A1
公开(公告)日：1995-01-04
申请号：EP94109636.4
申请日：1994-06-22
IPC分类号： G06F11/26
CPC分类号： G06F11/22
摘要： A first test circuit (21) is connected to one end of a first wiring line (40), and a second test circuit (22) is connected to one end of a second wiring line (41). The second wiring line (41) serves as a data bus. N-channel MOS transistors (50, 51), connected in series, are provided between the first and second wiring lines (40, 41) and located below a third wiring line (42). The transistors (50, 51) are set in an conductive state by a gate control signal (TEST) from a test control circuit (53) in a test mode, and are set in an OFF state in a normal operation mode. In the normal operation mode, the capacitance between the first and second wiring lines (40, 41) is small and does not adversely affect the operation speed of an integrated circuit.
摘要翻译： 第一测试电路（21）连接到第一布线（40）的一端，第二测试电路（22）连接到第二布线（41）的一端。 第二布线（41）用作数据总线。 串联连接的N沟道MOS晶体管（50,51）设置在第一和第二布线（40,41）之间并位于第三布线（42）的下方。 晶体管（50,51）在测试模式下通过来自测试控制电路（53）的门控制信号（TEST）设置在导通状态，并且在正常操作模式中被设置为OFF状态。 在正常工作模式中，第一和第二布线（40,41）之间的电容小，对集成电路的运行速度没有不利影响。
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公开(公告)号：EP0499985A3
公开(公告)日：1992-09-16
申请号：EP92102522.7
申请日：1992-02-14
发明人： Saeki, Yukihiro, c/o Intellectual Property Div. , Matsumoto, Osamu, c/o Intellectual Property Div. , Yoshida, Masayuki, c/o Intellectual Property Div. , Mizutani, Takahide, c/o Intellectual Property Div. , Chida, Nobuyoshi, c/o Intellectual Property Div. , Shigematsu, Tomohisa, c/o Intellectual Prop. Div. , Uemura, Teruo, c/o Intellectual Property Div. , Toyoda, Kenji, c/o Intellectual Property Div. , Takamura, Hiroyuki, c/o Intellectual Property Div.
IPC分类号： H01L21/336 , H01L21/82
CPC分类号： H01L27/11521 , Y10S148/106
摘要： A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film (22) and a gate oxide film (21) on a semiconductor substrate (20), depositing a first conductive layer (23) on an entire surface of the resultant structure, selectively etching the first conductive layer (23) located in a region other than an element region, oxidation of the entire surface of the resultant structure, depositing a second conductive layer (27) on an entire surface of the resultant structure, and etching the first conductive layer (23), the oxide film (26), and the second conductive layer (27) using the same mask to form a plurality of floating gates by the first conductive layer (23) and to form a plurality of control gates by the second conductive layer (27), wherein the step of selectively etching the first conductive layer (23) includes the first etching step of forming cell slits (24) for separating the plurality of floating gates from each other and the second etching step of forming removed regions (25) each of which includes only one end of each of the plurality of control gates.
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3.发明公开Manufacturing method of semiconductor memory device 失效Verfahren zum Herstellen einer Halbleiterspeicheranordnung。
公开(公告)号：EP0499985A2
公开(公告)日：1992-08-26
申请号：EP92102522.7
申请日：1992-02-14
发明人： Saeki, Yukihiro, c/o Intellectual Property Div. , Matsumoto, Osamu, c/o Intellectual Property Div. , Yoshida, Masayuki, c/o Intellectual Property Div. , Mizutani, Takahide, c/o Intellectual Property Div. , Chida, Nobuyoshi, c/o Intellectual Property Div. , Shigematsu, Tomohisa, c/o Intellectual Prop. Div. , Uemura, Teruo, c/o Intellectual Property Div. , Toyoda, Kenji, c/o Intellectual Property Div. , Takamura, Hiroyuki, c/o Intellectual Property Div.
IPC分类号： H01L21/336 , H01L21/82
CPC分类号： H01L27/11521 , Y10S148/106
摘要： A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film (22) and a gate oxide film (21) on a semiconductor substrate (20), depositing a first conductive layer (23) on an entire surface of the resultant structure, selectively etching the first conductive layer (23) located in a region other than an element region, oxidation of the entire surface of the resultant structure, depositing a second conductive layer (27) on an entire surface of the resultant structure, and etching the first conductive layer (23), the oxide film (26), and the second conductive layer (27) using the same mask to form a plurality of floating gates by the first conductive layer (23) and to form a plurality of control gates by the second conductive layer (27), wherein the step of selectively etching the first conductive layer (23) includes the first etching step of forming cell slits (24) for separating the plurality of floating gates from each other and the second etching step of forming removed regions (25) each of which includes only one end of each of the plurality of control gates.
摘要翻译： 半导体存储器件的制造方法包括以下步骤：在半导体衬底（20）上选择性地形成场氧化物膜（22）和栅氧化膜（21），在第一导电层（23）的整个表面上沉积第一导电层 所得到的结构，选择性地蚀刻位于元件区域以外的区域的第一导电层（23），所得结构的整个表面的氧化，在所得结构的整个表面上沉积第二导电层（27） 并使用相同的掩模蚀刻第一导电层（23），氧化膜（26）和第二导电层（27），以由第一导电层（23）形成多个浮栅，并形成多个 通过第二导电层（27）的控制栅极，其中选择性蚀刻第一导电层（23）的步骤包括形成用于将多个浮置栅极彼此分离的单元狭缝（24）的第一蚀刻步骤 形成除去区域（25）的第二蚀刻步骤，每个蚀刻步骤仅包括多个控制栅极中的每一个的一端。
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公开(公告)号：EP0385469A3
公开(公告)日：1992-04-08
申请号：EP90104010.5
申请日：1990-03-01
发明人： Takiba, Akira, c/o Intellectual Property Div. , Matsumoto, Osamu, c/o Intellectual Property Div. , Saeki, Yukihiro, c/o Intellectual Property Div.
摘要： A potential detecting circuit comprises a first MOS transistor (N6, P6) of a first conductivity type whose drain receives an input potential whose absolute which is equal to or lower, in absolute value, than a second potential whose absolute value is higher than that of a first potential, a second MOS transistor of a second conductivity type whose source is connected to the source of the first transistor and gate receives the first potential, a third MOS transistor (N11, P11) of the first conductivity type whose source is connected to the second MOS transistor (P5, N5), source receives a reference potential whose absolute value is lower than that of the first potential, and gate receives the first potential, a detecting potential control block for applying to the first MOS transistor a potential varying in accordance with the input potential, and a potential detect output terminal for providing a detected potential, the potential detect output terminal being a junction between the drains of the second and third MOS transistors.
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公开(公告)号：EP0632385B1
公开(公告)日：1998-11-04
申请号：EP94109636.4
申请日：1994-06-22
IPC分类号： G06F11/26
CPC分类号： G06F11/22
摘要： A first test circuit (21) is connected to one end of a first wiring line (40), and a second test circuit (22) is connected to one end of a second wiring line (41). The second wiring line (41) serves as a data bus. N-channel MOS transistors (50, 51), connected in series, are provided between the first and second wiring lines (40, 41) and located below a third wiring line (42). The transistors (50, 51) are set in an conductive state by a gate control signal (TEST) from a test control circuit (53) in a test mode, and are set in an OFF state in a normal operation mode. In the normal operation mode, the capacitance between the first and second wiring lines (40, 41) is small and does not adversely affect the operation speed of an integrated circuit.
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6.发明公开Programmable logic unit circuit and programmable logic circuit 失效Programmierbare logische Einheit und Schaltung。
公开(公告)号：EP0512536A2
公开(公告)日：1992-11-11
申请号：EP92107697.2
申请日：1992-05-07
发明人： Saeki, Yukihiro, c/o Intellectual Property Div. , Muroga, Hiroki, c/o Intellectual Property Div. , Shigematsu, Tomohisa c/o Intellectual Property Div , Hibi, Toshio, c/o Intellectual Property Div. , Kawahara, Yasuo, c/o Intellectual Property Div. , Maru, Kazunao, c/o Intellectual Property Div. , Austin, Kenneth , Work, Gordon Stirling , Wedgwood, Darren Martin
IPC分类号： H03K19/177
CPC分类号： H03K19/17764 , G11C11/404 , G11C11/412 , H03K19/17704 , H03K19/17728 , H03K19/1774
摘要： A programmable logic unit circuit comprising a data memory circuit (10), a combinational logic circuit (13) supplied with at least two input signals, two input select circuits (11,12) for, based on the stored data in the data memory circuit (10), selecting the two input signals supplied to the combinational logic circuit (13) from more than two input signals, a clock-synchronized circuit (14) for supplying the output signal from the combinational logic circuit (13) in synchronization with a clock signal, and a 3-state-output type output select circuit (16) for selecting either the output signal of the combinational logic circuit (13) or the output signal of the clock-synchronized circuit (14), depending on the stored data in the data memory circuit (10).
摘要翻译： 一种可编程逻辑单元电路，包括数据存储电路（10），提供有至少两个输入信号的组合逻辑电路（13），用于基于数据存储电路中存储的数据的两个输入选择电路（11,12） 从多于两个的输入信号中选择提供给组合逻辑电路的两个输入信号;时钟同步电路（14），用于与时钟信号同步地提供来自组合逻辑电路的输出信号， 输出型输出选择电路（16），用于根据数据存储电路中存储的数据选择组合逻辑电路的输出信号或时钟同步电路的输出信号。
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公开(公告)号：EP0384429A2
公开(公告)日：1990-08-29
申请号：EP90103330.8
申请日：1990-02-21
发明人： Saeki, Yukihiro, c/o Intellectual Property Div. , Suzuki, Yasoji, c/o Intellectual Property Div.
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17704 , H03K19/1731
摘要： A programmable logic circuit for deriving a logic output of first and second signals includes a 2-input logic gate (2) for deriving a logic output of two signals. The 2-input logic gate (2) is constituted by connecting two 3-state circuits (1₁, 1₂) in a wired OR configuration. One (1₁) of the 3-state circuits includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives an inverted signal ( B ) of the second signal, and the data output terminal is set to one of three states of "1", "0", and the high impedance. Likewise, the other 3-state circuit (1₂) includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives the second signal (B), and the data output terminal is set to one of three states of "1", "0", and the high impedance. Each of the data input terminals of the 3-state circuits (1₁, 1₂) is supplied with a desired one of the first signal (A), an inverted signal ( A ) of the first signal, a "0" level signal, and a "1" level signal in a programmable fashion. Various logic gates can be realized by programming the supplying states of the four signals.
摘要翻译： 用于导出第一和第二信号的逻辑输出的可编程逻辑电路包括用于导出两个信号的逻辑输出的2-输入逻辑门（2）。 2输入逻辑门（2）是通过以线或配置连接两个三态电路（1 1，1 2）而构成的。 三态电路中的一个（1 1）包括数据输入端，输出控制输入端和数据输出端，输出控制输入端接收第二信号的反相信号（B），并设置数据输出端 到“1”，“0”和高阻抗三种状态中的一种。 类似地，另一个三态电路（1 2）包括数据输入端，输出控制输入端和数据输出端，输出控制输入端接收第二信号（B），数据输出端设置为 “1”，“0”和高阻抗三种状态。 给三态电路（1 1，1 2）的每个数据输入端提供第一信号（A），第一信号的反相信号（A），“0”电平信号和 以可编程方式的“1”电平信号。 通过编程四个信号的供应状态可以实现各种逻辑门。
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公开(公告)号：EP0438050B1
公开(公告)日：1996-05-01
申请号：EP91100033.9
申请日：1991-01-02
发明人： Kondo, Hitoshi, c/o Intellectual Property Div. , Yamamoto, Tetsuya, c/o Intellectual Property Div. , Saeki, Yukihiro, c/o Intellectual Property Div.
IPC分类号： G11C16/06
CPC分类号： G11C16/105 , G11C16/102 , G11C16/34
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公开(公告)号：EP0438050A2
公开(公告)日：1991-07-24
申请号：EP91100033.9
申请日：1991-01-02
发明人： Kondo, Hitoshi, c/o Intellectual Property Div. , Yamamoto, Tetsuya, c/o Intellectual Property Div. , Saeki, Yukihiro, c/o Intellectual Property Div.
IPC分类号： G11C16/06
CPC分类号： G11C16/105 , G11C16/102 , G11C16/34
摘要： An EPROM integrated circuit (20) includes a plurality of banks. When a data write operation is to be performed for this EEPROM integrated circuit (20), a bank which is used once is not used again, but the operation is constantly performed for new banks. In order to select a bank, a write number storage area (21) is provided in the EPROM integrated circuit (20), and the contents of the write number storage area (21) are updated by a write number updating circuit (29) each time the write operation is performed for a new bank.
摘要翻译： EPROM集成电路（20）包括多个存储体。 当对该EEPROM集成电路（20）执行数据写入操作时，一次使用的存储体不再被使用，但是对于新的存储体不断地执行操作。 为了选择存储体，在EPROM集成电路（20）中设置写入存储区域（21），写入数量存储区域（21）的内容由写入数量更新电路（29）进行更新 对新银行执行写入操作的时间。
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公开(公告)号：EP0385469A2
公开(公告)日：1990-09-05
申请号：EP90104010.5
申请日：1990-03-01
发明人： Takiba, Akira, c/o Intellectual Property Div. , Matsumoto, Osamu, c/o Intellectual Property Div. , Saeki, Yukihiro, c/o Intellectual Property Div.
摘要： A potential detecting circuit comprises a first MOS transistor (N6, P6) of a first conductivity type whose drain receives an input potential whose absolute which is equal to or lower, in absolute value, than a second potential whose absolute value is higher than that of a first potential, a second MOS transistor of a second conductivity type whose source is connected to the source of the first transistor and gate receives the first potential, a third MOS transistor (N11, P11) of the first conductivity type whose source is connected to the second MOS transistor (P5, N5), source receives a reference potential whose absolute value is lower than that of the first potential, and gate receives the first potential, a detecting potential control block for applying to the first MOS transistor a potential varying in accordance with the input potential, and a potential detect output terminal for providing a detected potential, the potential detect output terminal being a junction between the drains of the second and third MOS transistors.
摘要翻译： 电位检测电路包括第一导电类型的第一MOS晶体管（N6，P6），其漏极接收绝对值等于或小于绝对值的绝对值大于第二绝对值的第二电位的输入电位 第一电位，第二导电类型的第二MOS晶体管，其源极连接到第一晶体管的源极并且栅极接收第一电位;第一导电类型的第三MOS晶体管（N11，P11），其源极连接到 所述第二MOS晶体管（P5，N5）的源极接收其绝对值低于所述第一电位的基准电位，并且所述栅极接收所述第一电位;检测电位控制块，用于向所述第一MOS晶体管施加电位变化 根据所述输入电位以及用于提供检测电位的电位检测输出端子，所述电位检测输出端子是所述电位检测输出端子 ns的第二和第三MOS晶体管。
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