A semiconductor memory chip architecture is described in which implementation of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2 n X4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.