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1.发明公开Memory device having asymmetrical CAS to data input/output mapping and applications thereof 失效存储器装置与CAS和数据输入/输出，和其应用之间是不对称的形成。
公开(公告)号：EP0657892A2
公开(公告)日：1995-06-14
申请号：EP94116320.6
申请日：1994-10-17
IPC分类号： G11C11/407 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1006
摘要： A semiconductor memory chip architecture is described in which implementation of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2 n X4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.
摘要翻译： 半导体存储系统包括可寻址存储器单元中的至少一个阵列，并解决单个存储器访问周期内的多个单元的装置。 提供两个时钟信号，和一个电路使第一奇数寻址到被访问的单元，并且使第二奇数加以解决访问的单元。 该电路响应于第一时钟信号，用于使第一奇数寻址到被访问的单元，以及用于使所述第二奇数个单元的第二时钟信号加以处理访问。 一个所述第一和第二奇数的是大于1。这两个时钟信号在相同的存储器访问周期的应用。 第一奇数数目可以是1和第二等于3，或者第一奇数是3，第二个是在第五
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2.发明公开Boosted drive system for master/local word line memory architecture 失效Antriebsverstärkersystemfürmit Haupt- / Nebenwortleitungen ausgestatteten Speicher。
公开(公告)号：EP0551598A2
公开(公告)日：1993-07-21
申请号：EP92120275.0
申请日：1992-11-27
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： An integrated boost and local word line drive system that enhances the speed of the word line drive without providing excessive voltage stresses to the driver devices. A charge reservoir (20) stores a boost voltage (BST) under the control of a charge pump (15) that is regulated by a voltage regulator (10). One of the local word lines (LWL) coupled to a selected master word line (MWL) is enabled by a driver (50) that receives the boost voltage (BST). The switching times and signal slew rates of the driver, as well as the boost voltage, are controlled to prevent excessive gate stresses in the support circuitry.
摘要翻译： 集成升压和本地字线驱动系统，可提高字线驱动的速度，而不会对驱动器设备造成过大的电压应力。 电荷贮存器（20）在由电压调节器（10）调节的电荷泵（15）的控制下存储升压电压（BST）。 耦合到所选主字线（MWL）的一个本地字线（LWL）由接收升压电压（BST）的驱动器（50）使能。 控制驱动器的切换时间和信号转换速率以及升压电压，以防止支持电路中的过大的栅极应力。
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公开(公告)号：EP0551598A3
公开(公告)日：1994-11-09
申请号：EP92120275.0
申请日：1992-11-27
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： An integrated boost and local word line drive system that enhances the speed of the word line drive without providing excessive voltage stresses to the driver devices. A charge reservoir (20) stores a boost voltage (BST) under the control of a charge pump (15) that is regulated by a voltage regulator (10). One of the local word lines (LWL) coupled to a selected master word line (MWL) is enabled by a driver (50) that receives the boost voltage (BST). The switching times and signal slew rates of the driver, as well as the boost voltage, are controlled to prevent excessive gate stresses in the support circuitry.
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公开(公告)号：EP0511560A3
公开(公告)日：1994-02-23
申请号：EP92106611.4
申请日：1992-04-16
发明人： Abadeer, Wagdi William , El-Kareh, Badih , Ellis, Wayne Frederick , Galbi, Duane Elmer , Hiltebeitel, Nathan Rafael , Tonti, William Robert , Watts, Josef Samuel
CPC分类号： G11C29/785 , G11C17/14 , G11C17/16
摘要： A programmable storage element for redundancy-programming includes a programmable antifuse circuit which includes a plurality of first resistors (F1a, F1b, F1c) and a switching circuit (Q Fa , Q Fb , Q Fc , Q Fd ) for coupling the first resistors in series in response to a plurality of first control signals (Ta, Tb, Tc, Td) and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programming of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.
摘要翻译： 用于冗余编程的可编程存储元件包括可编程反熔丝电路，其包括多个第一电阻器（F1a，F1b，F1c）以及用于响应于第一电阻器串联耦合第一电阻器的开关电路（QFa，QFb，QFc，QFd） 多个第一控制信号（Ta，Tb，Tc，Td），并响应于多个第二控制信号并联耦合第一电阻器以允许对第一电阻器进行编程;以及感测电路，用于确定 第一个电阻已经编程。 通过比较第一电阻器上的第一电压降与第二电阻器上的第二电压降来确定第一电阻器的状态。 每个第一电阻器是非硅化多晶硅导体，当预定的阈值电流被施加最小时间段时，其具有不可逆的电阻降低。
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5.发明公开Zag fuse for reduced blow-current applications 失效Zickzack-SchmelzvorrichtungfürAnwendungen mit reduziertem Schmelzstrom。
公开(公告)号：EP0563852A1
公开(公告)日：1993-10-06
申请号：EP93105170.0
申请日：1993-03-29
发明人： Galbi, Duane Elmer , Guthrie, William Hewlett , Kiehl, Oliver , Mandelman, Jack Allan , Watts, Josef Samuel
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse, having reduced blow-current requirements thereby minimizing the power supply voltage and chip area required for the driver transistors, has a geometry which is characterized by an essentially uniform width dimension throughout the primary axis of the fuse link but having at least one approximately right angle bend in the fuse link. The fuse can be blown open with approximately 10% of the input current density required for a straight fuse of equal cross-sectional area. The reason for this is that, due to current crowding, the current density is accentuated at the inside corner of the bend. As the input current to the fuse is increased, a current density is reached at the inside corner which causes the fuse material to melt. A notch forms at the inside corner. The fuse geometry altered by the notching causes even more severe current crowding at the notches, and this in turn makes the melting propagate across the width of the fuse. The predictability of the point of fuse blow out allows even greater circuit densities while minimizing the possibility of accidental damage to adjacent devices.
摘要翻译： 具有降低的电流要求从而使驱动晶体管所需的电源电压和芯片面积最小化的保险丝具有几何形状，其特征在于在熔丝链的整个主轴上具有基本均匀的宽度尺寸，但具有至少一个约 熔断体直角弯曲。 熔断器可以吹开大约10％的输入电流密度所需的直流熔断器等截面积。 这样做的原因是，由于目前的拥挤，电流密度在弯曲的内部角落被强化。 当保险丝的输入电流增加时，在内角处达到电流密度，导致熔丝材料熔化。 内角处形成凹痕。 通过开槽改变的保险丝几何在槽口处产生更严重的电流拥挤，这又导致熔化物在保险丝的宽度上传播。 保险丝熔断点的可预测性允许更大的电路密度，同时最小化对相邻设备的意外损坏的可能性。
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6.发明公开Memory device having asymmetrical CAS to data input/output mapping and applications thereof 失效存储器装置与CAS和数据输入/输出，和其应用之间是不对称的形成。
公开(公告)号：EP0657892A3
公开(公告)日：1996-01-17
申请号：EP94116320.6
申请日：1994-10-17
IPC分类号： G11C11/407 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1006
摘要： A semiconductor memory chip architecture is described in which implementation of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2 n X4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.
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公开(公告)号：EP0555539A3
公开(公告)日：1993-11-18
申请号：EP92120401.2
申请日：1992-11-28
IPC分类号： G05F3/24
CPC分类号： H03K17/145 , G05F3/247
摘要： A voltage reference circuit that produces an output offset from a supply voltage by approximately two volts, the output (VOUT) being relatively stable in the face of vacillations in the external power supplies. The first leg of the circuit utilizes devices (TPH1, TP1, TN1) having differing Vt's to produce an internal reference of one volt below Vdd. In a first embodiment of the invention, the second leg has a first device (TP2), wherein the gate receives the internal reference and the source is at the high power supply (VDD), and a high Vt diode connected device (TPH2). The two devices (TP2, TPH2) are matched to have the same overdrive current, which is at a voltage that is a function of the difference between the gate-to-source voltage of the first device and the threshold voltage of the first device. Thus, the output is a function of the overdrive to, and the diode drop across, the second high-Vt device.
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8.发明公开Stable voltage reference circuit with high Vt devices 失效Referenzspannungsschaltung mit hohen Schwellenspannunganlagen。
公开(公告)号：EP0555539A2
公开(公告)日：1993-08-18
申请号：EP92120401.2
申请日：1992-11-28
IPC分类号： G05F3/24
CPC分类号： H03K17/145 , G05F3/247
摘要： A voltage reference circuit that produces an output offset from a supply voltage by approximately two volts, the output (VOUT) being relatively stable in the face of vacillations in the external power supplies. The first leg of the circuit utilizes devices (TPH1, TP1, TN1) having differing Vt's to produce an internal reference of one volt below Vdd. In a first embodiment of the invention, the second leg has a first device (TP2), wherein the gate receives the internal reference and the source is at the high power supply (VDD), and a high Vt diode connected device (TPH2). The two devices (TP2, TPH2) are matched to have the same overdrive current, which is at a voltage that is a function of the difference between the gate-to-source voltage of the first device and the threshold voltage of the first device. Thus, the output is a function of the overdrive to, and the diode drop across, the second high-Vt device.
摘要翻译： 电压参考电路产生从电源电压输出偏移约两伏特，输出（VOUT）在面对外部电源的摆动时相对稳定。 电路的第一段利用具有不同Vt的器件（TPH1，TP1，TN1）产生低于Vdd 1伏的内部基准电压。 在本发明的第一实施例中，第二支路具有第一器件（TP2），其中栅极接收内部基准电压，并且源极处于高电源（VDD），以及高Vt二极管连接器件（TPH2）。 两个器件（TP2，TPH2）被匹配以具有相同的过驱动电流，其是处于第一器件的栅极 - 源极电压与第一器件的阈值电压之间的差的函数的电压。 因此，输出是第二个高Vt器件的过驱动和二极管压降的函数。
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公开(公告)号：EP0511560A2
公开(公告)日：1992-11-04
申请号：EP92106611.4
申请日：1992-04-16
发明人： Abadeer, Wagdi William , El-Kareh, Badih , Ellis, Wayne Frederick , Galbi, Duane Elmer , Hiltebeitel, Nathan Rafael , Tonti, William Robert , Watts, Josef Samuel
CPC分类号： G11C29/785 , G11C17/14 , G11C17/16
摘要： A programmable storage element for redundancy-programming includes a programmable antifuse circuit which includes a plurality of first resistors (F1a, F1b, F1c) and a switching circuit (Q Fa , Q Fb , Q Fc , Q Fd ) for coupling the first resistors in series in response to a plurality of first control signals (Ta, Tb, Tc, Td) and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programming of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.
摘要翻译： 用于冗余编程的可编程存储元件包括可编程反熔丝电路，其包括多个第一电阻器（F1a，F1b，F1c）和用于响应于第一电阻器串联耦合第一电阻器的开关电路（QFa，QFb，QFc，QFd） 多个第一控制信号（Ta，Tb，Tc，Td），并且用于响应于多个第二控制信号并联耦合第一电阻器以允许编程第一电阻器;以及感测电路，用于确定是否 第一个电阻已编程。 第一电阻器的状态通过将第一电阻器两端的第一电压降与第二电阻器上的第二电压降进行比较来确定。 第一电阻器中的每一个是非极性多晶硅导体，当预定阈值电流施加最小时间时，其具有不可逆电阻降低。
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