A data output buffer circuit for a semiconductor integrated circuit having a plurality of output buffer circuits (OB) where the output buffer circuits (OB) have serially connected first and second switching means (Tr1, Tr2), a timing signal input terminal for receiving a timing signal (T), timing switch means (Tr41) for being turned on by said timing signal (T), and a delay circuit (D1 ∼ Dn) connected between said timing switch means (Tr41) and the control terminals of the first and second switching means (Tr1, Tr2), where the delay times of the respective delay circuits (Dx) of at least two output buffer circuits are different from one another.