公开(公告)号：EP0432790B1

公开(公告)日：1996-10-16

申请号：EP90124192.7

申请日：1990-12-14

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

发明人： Yano, Junji, B-105, Shellhouse Myorenji ,  Miyawaki, Tsukasa ,  Atoh, Masami ,  Gotou, Masakazu, Toshiba Dai-2 Wakakusa Ryo, 4-6 ,  Iwashita, Masakazu ,  Kaji, Michio

IPC分类号： G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/108

公开(公告)号：EP0432790A3

公开(公告)日：1992-09-30

申请号：EP90124192.7

申请日：1990-12-14

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

发明人： Yano, Junji, B-105, Shellhouse Myorenji ,  Miyawaki, Tsukasa ,  Atoh, Masami ,  Gotou, Masakazu, Toshiba Dai-2 Wakakusa Ryo, 4-6 ,  Iwashita, Masakazu ,  Kaji, Michio

IPC分类号： G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/108

摘要： A data output buffer circuit for a semiconductor integrated circuit, including an input terminal for receiving an input data (IN); an output buffer (OB) having first and second switching circuits (Tr1, Tr2) serially connected between two high and low power source terminals (V cc , V ss ), each of the first and second switching circuits (Tr1, Tr2) having a control terminal for turning on and off each of the first and second switching circuits (Tr1, Tr2) upon reception of a control signal to the control terminal; an output terminal connected to an interconnection between the first and second switching circuits (Tr1, Tr2); and a through current blocking circuit (10; 20; 30) for applying a first control signal to the control terminal of each of the first and second switching circuits (Tr1, Tr2) when the level of the input data (IN) is changed, so as to turn off both the first and second switching circuits (Tr1, Tr2), and thereafter applying a second control signal to the control terminal of each of the first and second switching circuits (Tr1, Tr2), so as to obtain an output signal corresponding to the input data. A data output buffer circuit for a semiconductor integrated circuit having a plurality of output buffer circuits, each output buffer circuit being constructed similar to the above output buffer circuit; wherein each output buffer circuit operates to output an output data for each of a plurality of input data to the external at the same time. A data output buffer circuit for a semiconductor integrated circuit wherein a first transistor (Tr21) of a first channel type and second and third transistor (Tr22, Tr23) of a second channel type are connected in series between a pair of power source terminals (V cc , V ss ), the gate of the first transistor (Tr21) and the gate of one of the second and third transistors (Tr22, Tr23) are connected to an input terminal (A), the input terminal (A) is connected via a delay circuit (DL2) to the gate of the other of the second and third transistors (Tr22, Tr23), and an interconnection between the first and second transistors (Tr21, Tr22) is connected to an output terminal (C).

公开(公告)号：EP0686975A1

公开(公告)日：1995-12-13

申请号：EP95113987.2

申请日：1990-12-14

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

发明人： Yano, Junji ,  Miyawaki, Tsukasa ,  Atoh, Masami ,  Gotou, Masakazu ,  Iwashita, Masakazu ,  Kaji, Michio

IPC分类号： G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/108

摘要： A data output buffer circuit for a semiconductor integrated circuit having a plurality of output buffer circuits (OB) where the output buffer circuits (OB) have serially connected first and second switching means (Tr1, Tr2), a timing signal input terminal for receiving a timing signal (T), timing switch means (Tr41) for being turned on by said timing signal (T), and a delay circuit (D1 ∼ Dn) connected between said timing switch means (Tr41) and the control terminals of the first and second switching means (Tr1, Tr2), where the delay times of the respective delay circuits (Dx) of at least two output buffer circuits are different from one another.

摘要翻译： 一种用于具有多个输出缓冲电路（OB）的半导体集成电路的数据输出缓冲电路，其中输出缓冲电路（OB）串联连接第一和第二开关装置（Tr1，Tr2），定时信号输入端子用于接收 定时信号（T），由所述定时信号（T）导通的定时开关装置（Tr41）以及连接在所述定时开关装置（Tr41）和第一和第二控制端子之间的延迟电路（D1 SIMILD Dn） 第二切换装置（Tr1，Tr2），其中至少两个输出缓冲电路的各个延迟电路（Dx）的延迟时间彼此不同。

公开(公告)号：EP0432790A2

公开(公告)日：1991-06-19

申请号：EP90124192.7

申请日：1990-12-14

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

发明人： Yano, Junji, B-105, Shellhouse Myorenji ,  Miyawaki, Tsukasa ,  Atoh, Masami ,  Gotou, Masakazu, Toshiba Dai-2 Wakakusa Ryo, 4-6 ,  Iwashita, Masakazu ,  Kaji, Michio

IPC分类号： G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/108

摘要： A data output buffer circuit for a semiconductor integrated circuit, including an input terminal for receiving an input data (IN); an output buffer (OB) having first and second switching circuits (Tr1, Tr2) serially connected between two high and low power source terminals (V cc , V ss ), each of the first and second switching circuits (Tr1, Tr2) having a control terminal for turning on and off each of the first and second switching circuits (Tr1, Tr2) upon reception of a control signal to the control terminal; an output terminal connected to an interconnection between the first and second switching circuits (Tr1, Tr2); and a through current blocking circuit (10; 20; 30) for applying a first control signal to the control terminal of each of the first and second switching circuits (Tr1, Tr2) when the level of the input data (IN) is changed, so as to turn off both the first and second switching circuits (Tr1, Tr2), and thereafter applying a second control signal to the control terminal of each of the first and second switching circuits (Tr1, Tr2), so as to obtain an output signal corresponding to the input data.
A data output buffer circuit for a semiconductor integrated circuit having a plurality of output buffer circuits, each output buffer circuit being constructed similar to the above output buffer circuit; wherein each output buffer circuit operates to output an output data for each of a plurality of input data to the external at the same time.
A data output buffer circuit for a semiconductor integrated circuit wherein a first transistor (Tr21) of a first channel type and second and third transistor (Tr22, Tr23) of a second channel type are connected in series between a pair of power source terminals (V cc , V ss ), the gate of the first transistor (Tr21) and the gate of one of the second and third transistors (Tr22, Tr23) are connected to an input terminal (A), the input terminal (A) is connected via a delay circuit (DL2) to the gate of the other of the second and third transistors (Tr22, Tr23), and an interconnection between the first and second transistors (Tr21, Tr22) is connected to an output terminal (C).

摘要翻译： 一种用于半导体集成电路的数据输出缓冲电路，包括用于接收输入数据（IN）的输入端子; 具有串联连接在两个高电源端子和低电源端子（Vcc，Vss）之间的第一和第二开关电路（Tr1，Tr2）的输出缓冲器（OB），第一和第二开关电路（Tr1，Tr2）中的每一个具有控制端子 用于在控制端子接收到控制信号时接通和断开第一和第二开关电路（Tr1，Tr2）中的每一个; 连接到第一和第二开关电路（Tr1，Tr2）之间的互连的输出端子; 以及当所述输入数据（IN）的电平改变时，将第一控制信号施加到所述第一和第二开关电路（Tr1，Tr2）中的每一个的控制端的通流阻塞电路（10; 20; 30） 以断开第一和第二开关电路（Tr1，Tr2），然后将第二控制信号施加到第一和第二开关电路（Tr1，Tr2）中的每一个的控制端，以便获得输出 信号对应于输入数据。 一种用于具有多个输出缓冲电路的半导体集成电路的数据输出缓冲电路，每个输出缓冲电路被构造成类似于上述输出缓冲电路; 其中每个输出缓冲器电路操作以将多个输入数据中的每一个的输出数据同时输出到外部。 一种用于半导体集成电路的数据输出缓冲电路，其中第一通道类型的第一晶体管（Tr21）和第二通道类型的第二和第三晶体管（Tr22，Tr23）串联连接在一对电源端子（Vcc ，Vss），第一晶体管（Tr21）的栅极和第二和第三晶体管（Tr22，Tr23）之一的栅极连接到输入端子（A），输入端子（A）经由延迟 电路（DL2）连接到第二和第三晶体管（Tr22，Tr23）中的另一个的栅极，并且第一和第二晶体管（Tr21，Tr22）之间的互连连接到输出端子（C）。