发明公开
EP0694976A3 Method of manufacturing an integrated circuit having p-MOSFETs with different channel widths 失效
制造具有不同沟道宽度的p-MOSFET的集成电路的方法

Method of manufacturing an integrated circuit having p-MOSFETs with different channel widths
摘要:
An anomalous threshold voltage dependence on channel width measured on 0.25 µm ground rule generation trench-isolated buried-channel p-MOSFETs is used to enhance circuit performance. According to the invention, a set of transistors (100) having a source node (30), a drain node (40) and a common gate (20) can be constructed. Each of the N transistors in the set (10-1 to 10-N) has a channel width (Wn) chosen to provide the desired V t . The total number N is chosen to have the required current for the application in question. As the channel width is reduced, the magnitude of the threshold voltage first decreases before the onset of the expected sharp rise in V t for widths narrower than 0.4 µm. Modeling shows that a "boron puddle" is created near the trench bounded edge as a result of transient enhanced diffusion (TED) during the gate oxidation step, which imposes a penalty on the off-current of narrow devices. TED is governed by interstitials produced by a deep phosphorus implant, used for latchup suppression, diffusing towards the trench sidewall and top surface of the device.
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