公开(公告)号：EP4312277A1

公开(公告)日：2024-01-31

申请号：EP22198983.3

申请日：2022-09-30

Applicant: United Microelectronics Corp.

Inventor： KUO, Chun-Liang ,  CHEN, Yen-Hsing ,  CHEN, Yen-Lun ,  SHEN, Ruei-Hong ,  YANG, Tsung-Mu ,  WANG, Yu-Ren

IPC: H01L29/778 ,  H01L21/337 ,  H01L29/207 ,  H01L29/36 ,  H01L29/10 ,  H01L29/20

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer (16) on a substrate (12), forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. The buffer layer further includes a bottom portion (18) having a first carbon concentration and a top portion (20) having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

公开(公告)号：EP4287263A1

公开(公告)日：2023-12-06

申请号：EP23173823.8

申请日：2023-05-17

Applicant: STMicroelectronics Crolles 2 SAS

Inventor： CHEVALIER, Pascal ,  FREGONESE, Sebastien ,  ZIMMER, Thomas

IPC: H01L29/735 ,  H01L21/331 ,  H01L29/417 ,  H01L29/08 ,  H01L29/40 ,  H01L29/36

Abstract: La présente description concerne un transistor bipolaire latéral (100) comprenant :
- une région d'émetteur (112) dopée d'un premier type de conductivité et présentant une première largeur (L12) ;
- une région de collecteur (116) dopée du premier type de conductivité, présentant une deuxième largeur (L16) supérieure à la première largeur et une concentration moyenne de dopage inférieure à la concentration moyenne de dopage de la région d'émetteur ;
- une région de base (114) entre les régions d'émetteur et de collecteur dopée du deuxième type de conductivité; lesdites régions étant disposées dans une couche de silicium (110) sur une couche d'isolant (104) sur un substrat (102) ;
- une région de substrat (106) dépourvue des couches de silicium et d'isolant, et positionnée du côté de la région de collecteur (116) ; et
- un circuit de polarisation (150) relié, et adapté à fournir, à la région de substrat une tension de polarisation de manière à moduler le dopage électrostatique de la région de collecteur.

公开(公告)号：EP4258364A1

公开(公告)日：2023-10-11

申请号：EP22166544.1

申请日：2022-04-04

Applicant: Infineon Technologies AG

Inventor： SCHULZE, Hans-Joachim ,  ELPELT, Rudolf ,  KONRATH, Jens Peter ,  SCHRAML, Konrad

IPC: H01L29/861 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/36

Abstract: A wide band gap semiconductor device (100) is proposed. The wide band gap semiconductor device (100) includes a semiconductor body (102) having a first surface (104) and a second surface (106) opposite to the first surface (104) along a vertical direction (y). The wide band gap semiconductor device (100) further includes a first region (108) of a first conductivity type adjoining at least partially the first surface (104), a drift region (110) of a second conductivity type, a highly doped second region (112) adjoining the second surface (106). The wide bandgap semiconductor device (100) further includes a buffer region (114) of the second conductivity type arranged between the drift region (110) and the highly doped second region (112). A vertical profile of a doping concentration (c) of the buffer region (114) includes at least one step (116) in a first section (1141) and is increasing approximately exponentially toward the second surface (106) in a second section (1442). The first section (1141) is arranged between the second section (1442) and the highly doped second region (112).

公开(公告)号：EP4250339A2

公开(公告)日：2023-09-27

申请号：EP22216033.5

申请日：2018-09-14

Applicant: Ascatron AB

Inventor： SCHÖNER, Adolf ,  RESHANOV, Sergey ,  THIERRY-JEBALI, Nicolas ,  ELAHIPANAH, Hossein

IPC: H01L21/329 ,  H01L21/337 ,  H01L29/808 ,  H01L29/872 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/36 ,  H01L29/10

Abstract: A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n1), b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions (p2) on the first layer (n1), if necessary with aid of removing parts of the added semiconductor material to form separated second regions (p2) on the first layer (n1), and c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer (n1) to form first regions (p1). It is possible to manufacture a grid with rounded corners as well as an upper part with a high doping level. It is possible to manufacture a component with efficient voltage blocking, high current conduction, low total resistance, high surge current capability, and fast switching.

公开(公告)号：EP4246594A1

公开(公告)日：2023-09-20

申请号：EP23154694.6

申请日：2023-02-02

Applicant: Ultraband Technologies Inc.

Inventor： WU, Chan-Shin

IPC: H01L29/778 ,  H01L29/36 ,  H01L29/20

Abstract: A semiconductor field-effect transistor contains an n-type doped layer (234) arranged close to the edge of the two-dimensional electron gas area (232G) in a channel layer (231); said n-type doped layer is arranged to adjust the distribution of electron concentration in the transistor, and to improve the RF linearity of the overall component; thereby not only the threshold voltage can be controlled through the adjustment of the charge, but the contact and series resistance can also be reduced.

公开(公告)号：EP4207310A1

公开(公告)日：2023-07-05

申请号：EP23151813.5

申请日：2018-12-12

Applicant: Wolfspeed, Inc.

Inventor： LICHTENWALNER, Daniel, Jenner ,  VAN BRUNT, Edward, Robert

IPC: H01L29/861 ,  H01L29/872 ,  H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L21/336 ,  H01L21/329 ,  H01L29/10

Abstract: A vertical semiconductor device includes a substrate, a buffer layer over the substrate, and a drift layer over the buffer layer. The substrate has a first doping type and a first doping concentration. The buffer layer has the first doping type and a second doping concentration that is less than the first doping concentration. The drift layer has the first doping type and a third doping concentration that is less than the second doping concentration.

公开(公告)号：EP4203059A1

公开(公告)日：2023-06-28

申请号：EP22203503.2

申请日：2022-10-25

Applicant: INTEL Corporation

Inventor： SHAH, Rushabh ,  GLASS, Glenn ,  HASAN, Mohammad ,  MURTHY, Anand ,  BOMBERGER, Cory

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00

Abstract: Cap layers (144) are formed on silicon germanium (SiGe) source/drain regions (140) of field-effect transistors, in particular FinFETs and GAA-FETs, to provide etch resistance to processing steps that can occur in a semiconductor manufacturing process between formation of the SiGe source/drain regions and metal contact (152) formation. The cap layers (144) comprise boron and are thin (e.g., 2 nm or less) to provide for a low metal contact resistance. The atomic concentration of boron in the cap layer is in a range of about 0.2-20%, and the cap layer preferably further comprises Si and Ge. In addition to providing etch resistance, the cap layer provides for a thermally stable contact resistance as the cap layer can prevent or limit the creation of voids in the SiGe layer by preventing or limiting the diffusion of germanium from the SiGe layer into the metal (148, 152) in subsequent annealing and other high-temperature processing steps.As metal-silicon-germanium region (168) is preferably formed between the source/drain region (140) and the metal contact (152).

公开(公告)号：EP4113624A1

公开(公告)日：2023-01-04

申请号：EP22180870.2

申请日：2022-06-24

Applicant: Huawei Technologies Co., Ltd.

Inventor： YANG, Wentao ,  DAI, Loucheng ,  SONG, Chaofan ,  HUANG, Boning ,  LIU, Zhihua

IPC: H01L29/739 ,  H01L29/32 ,  H01L29/36 ,  H01L21/265 ,  H01L21/331

Abstract: Embodiments of this application disclose a semiconductor device, a related chip, and a preparation method. The semiconductor device includes an N-type drift layer and an N-type field stop layer adjacent to the N-type drift layer. A density of free electrons at the N-type field stop layer is higher than a density of free electrons at the N-type drift layer. The N-type field stop layer includes a first impurity particle and a second impurity particle doped with the first impurity particle, and a radius of the second impurity particle is greater than a radius of the first impurity particle. In the N-type field stop layer, an injection density of the first impurity particle in a region adjacent to the N-type drift layer is higher than an injection density of the first impurity particle in any other region. The foregoing structure is used, to effectively alleviate a situation in which the semiconductor device generates an excessively high peak voltage in a circuit with a large parasitic inductance when the semiconductor device is turned off.

公开(公告)号：EP3970195A1

公开(公告)日：2022-03-23

申请号：EP20728420.9

申请日：2020-05-14

Applicant: mi2-factory GmbH

Inventor： CSATO, Constantin ,  KRIPPENDORF, Florian

IPC: H01L29/08 ,  H01J37/317 ,  H01L21/04 ,  H01L21/266 ,  H01L29/36 ,  H01L29/78 ,  H01L29/06 ,  H01L21/336

公开(公告)号：EP3925009A1

公开(公告)日：2021-12-22

申请号：EP21706284.3

申请日：2021-02-22

Applicant: ABB Power Grids Switzerland AG

Inventor： WIKSTROEM, Tobias ,  VEMULAPATI, Umamaheswara

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/332 ,  H01L29/744 ,  H01L29/36 ,  H01L29/423