发明公开
- 专利标题: FAULT RESILIENT/FAULT TOLERANT COMPUTING
- 专利标题(中): 故障弹性/容错计算
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申请号: EP95902615.0申请日: 1994-11-15
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公开(公告)号: EP0731945A1公开(公告)日: 1996-09-18
- 发明人: BISSETT, Thomas, D. , FIORENTINO, Richard, D. , GLORIOSO, Robert, M. , MCCAULEY, Diane, T. , MCCOLLUM, James, D. , TREMBLAY, Glenn, A. , TROIANI, Mario
- 申请人: MARATHON TECHNOLOGIES CORPORATION
- 申请人地址: 70 Birch Hill Road Stow, MA 01775 US
- 专利权人: MARATHON TECHNOLOGIES CORPORATION
- 当前专利权人: MARATHON TECHNOLOGIES CORPORATION
- 当前专利权人地址: 70 Birch Hill Road Stow, MA 01775 US
- 代理机构: Blatchford, William Michael, et al
- 优先权: US19930159783 19931201
- 国际公布: WO1995015529 19950608
- 主分类号: G06F11
- IPC分类号: G06F11 ; G06F1 ; G06F13 ; G06F15
摘要:
A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).
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