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    HYBRID MICROPROCESSOR AND PROGRAMMABLE LOGIC DEVICE (PLD)- BASED ARCHITECTURE INCLUDING INTER PROCESSOR COMMUNICATION
    8.
    发明公开
    HYBRID MICROPROCESSOR AND PROGRAMMABLE LOGIC DEVICE (PLD)- BASED ARCHITECTURE INCLUDING INTER PROCESSOR COMMUNICATION 审中-公开

    公开(公告)号：EP4456433A1

    公开(公告)日：2024-10-30

    申请号：EP24168451.3

    申请日：2024-04-04

    申请人： Hamilton Sundstrand Corporation

    发明人： MADATHIKANDAM, Rajesh ,  HILL, Robin ,  POTTER, Stephen ,  VIJAY, Ashish ,  KRISHNA, Rajeeva ,  THANGAVEL, Anitha

    IPC分类号： H03K19/17732 ,  G06F15/78

    摘要： A microprocessor-PLD hybrid architecture includes an IPC microprocessor (102) and a PLD (150) in signal communication with the IPC microprocessor (102) via an IPC interface (104). The IPC microprocessor (102) outputs a data read command to initiate a data read operation or a data write command. The PLD includes a plurality of PLD modules (154a-154n) that store data and a bus controller (152). The bus controller (152) communicates with the plurality of PLD modules (154a-154n) via a plurality of PLD interfaces (170) and is configured to sequentially execute a set of bus controller instructions (166). The bus controller (152) reads data from a target PLD module from among the plurality of PLD modules (154a-154n) in response to receiving the data read command, and transfers the data to the IPC microprocessor (102). The bus controller (152) receives data from the IPC microprocessor (102) and stores the data in a target PLD module from among the plurality of PLD modules (154a-154n) in response to receiving the data write command.

    COMPUTING SYSTEM, METHOD AND APPARATUS, AND ACCELERATION DEVICE
    9.
    发明公开
    COMPUTING SYSTEM, METHOD AND APPARATUS, AND ACCELERATION DEVICE 审中-公开

    公开(公告)号：EP4455898A1

    公开(公告)日：2024-10-30

    申请号：EP23739931.6

    申请日：2023-01-06

    申请人： Huawei Technologies Co., Ltd.

    发明人： LIU, Haocheng ,  ZHU, Qi ,  CUI, Baolong ,  WANG, Haijiang

    IPC分类号： G06F15/163

    摘要： A computing system, method, and apparatus, and an acceleration device are provided. A computing system (100) includes a host device (110) and an acceleration device (120). The host device (110) is in a communication connection with the acceleration device (120), the acceleration device is coupled to a memory (112), and the memory (112) stores first data required by a to-be-processed service. The host device (110) is configured to send invocation information to the acceleration device (120), where the invocation information indicates a storage address of the first data. The acceleration device (120) is configured to receive the invocation information sent by the host device (110), obtain the first data from the memory based on the storage address, and perform the to-be-processed task based on the first data to obtain a processing result. The host device (110) notifies the acceleration device (120) of the storage address, and the acceleration device (120) directly obtains the data from the memory (112) based on the storage address, so that the host device (110) is prevented from obtaining the data from the memory (112), to reduce a data transmission amount.