发明公开
- 专利标题: Delay-type FM demodulation circuit
- 专利标题(中): Verzögerungsdemodulation电路,用于FM信号
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申请号: EP96116777.2申请日: 1996-10-18
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公开(公告)号: EP0769846A3公开(公告)日: 1999-01-13
- 发明人: Adachi, Michihiro, c/o Intel Prop Div K.K. Toshiba
- 申请人: KABUSHIKI KAISHA TOSHIBA
- 申请人地址: 72, Horikawa-cho, Saiwai-ku Kawasaki-shi JP
- 专利权人: KABUSHIKI KAISHA TOSHIBA
- 当前专利权人: KABUSHIKI KAISHA TOSHIBA
- 当前专利权人地址: 72, Horikawa-cho, Saiwai-ku Kawasaki-shi JP
- 代理机构: Zangs, Rainer E., Dipl.-Ing.
- 优先权: JP271190/95 19951019
- 主分类号: H03D3/06
- IPC分类号: H03D3/06
摘要:
A delay-type FM demodulation circuit of this invention has an object to satisfactorily remove a harmonic wave in an arithmetic calculation output signal even if an LPF having relatively moderate stopping characteristics is used. The delay-type FM demodulation circuit includes first to third delay circuits (12 - 14) for obtaining first to third signals (S13 - S15) obtained by times (e.g., 1/8, 1/4, and 3/8) which sequentially increase within a time shorter than 1/2 which is a signal period obtained when an FM-modulated input signal (S12) is positively deviated by a maximum frequency, a first multiplication circuit (15) for multiplying the input signal and the first signal, a second multiplication circuit (16) for multiplying the second signal and the third signal, and an addition circuit (17) for adding an output signal (S16) from the first multiplication circuit and an output signal (S17) from the second multiplication circuit.
公开/授权文献
- EP0769846B1 Delay-type FM demodulation circuit 公开/授权日:2001-07-11
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