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公开(公告)号：EP0769846A3
公开(公告)日：1999-01-13
申请号：EP96116777.2
申请日：1996-10-18
IPC分类号： H03D3/06
CPC分类号： H03D3/06
摘要： A delay-type FM demodulation circuit of this invention has an object to satisfactorily remove a harmonic wave in an arithmetic calculation output signal even if an LPF having relatively moderate stopping characteristics is used. The delay-type FM demodulation circuit includes first to third delay circuits (12 - 14) for obtaining first to third signals (S13 - S15) obtained by times (e.g., 1/8, 1/4, and 3/8) which sequentially increase within a time shorter than 1/2 which is a signal period obtained when an FM-modulated input signal (S12) is positively deviated by a maximum frequency, a first multiplication circuit (15) for multiplying the input signal and the first signal, a second multiplication circuit (16) for multiplying the second signal and the third signal, and an addition circuit (17) for adding an output signal (S16) from the first multiplication circuit and an output signal (S17) from the second multiplication circuit.
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公开(公告)号：EP0769846A2
公开(公告)日：1997-04-23
申请号：EP96116777.2
申请日：1996-10-18
IPC分类号： H03D3/06
CPC分类号： H03D3/06
摘要： A delay-type FM demodulation circuit of this invention has an object to satisfactorily remove a harmonic wave in an arithmetic calculation output signal even if an LPF having relatively moderate stopping characteristics is used. The delay-type FM demodulation circuit includes first to third delay circuits (12 - 14) for obtaining first to third signals (S13 - S15) obtained by times (e.g., 1/8, 1/4, and 3/8) which sequentially increase within a time shorter than 1/2 which is a signal period obtained when an FM-modulated input signal (S12) is positively deviated by a maximum frequency, a first multiplication circuit (15) for multiplying the input signal and the first signal, a second multiplication circuit (16) for multiplying the second signal and the third signal, and an addition circuit (17) for adding an output signal (S16) from the first multiplication circuit and an output signal (S17) from the second multiplication circuit.
摘要翻译： 本发明的延迟型FM解调电路具有即使使用具有相对中等的停止特性的LPF也能令人满意地去除算术计算输出信号中的谐波的目的。 延迟型FM解调电路包括第一至第三延迟电路（12-14），用于获得按顺序（例如，1/8，1/4和3/8）顺序获得的第一至第三信号（S13-S15） 在短于作为FM调制输入信号（S12）正向偏离最大频率时获得的信号周期的1/2的时间内增加，用于将输入信号与第一信号相乘的第一乘法电路（15） 用于将第二信号和第三信号相乘的第二乘法电路（16）以及用于将来自第一乘法电路的输出信号（S16）与来自第二乘法电路的输出信号（S17）相加的加法电路（17）。
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