发明公开
- 专利标题: Viterbi decoding
- 专利标题(中): 维特比译码
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申请号: EP97302112.4申请日: 1997-03-26
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公开(公告)号: EP0798867A3公开(公告)日: 2000-09-27
- 发明人: Wakamatsu, Masataka
- 申请人: SONY CORPORATION
- 申请人地址: 6-7-35 Kitashinagawa Shinagawa-ku Tokyo 141 JP
- 专利权人: SONY CORPORATION
- 当前专利权人: SONY CORPORATION
- 当前专利权人地址: 6-7-35 Kitashinagawa Shinagawa-ku Tokyo 141 JP
- 代理机构: Williams, Janice
- 优先权: JP7384796U 19960328
- 主分类号: H03M13/00
- IPC分类号: H03M13/00
摘要:
Survivor sequences information is supplied to a RAM 61-1 and a RAM 61-2 as an input Din. The RAM 61-1 and the RAM 61-2 perform an interleaving operation and store the survivor sequences information alternately in accordance with a clock CK1 and a clock CK2 differing in phase from the clock CK1 by half a period. The phases of the clock CK1 and the phase of the clock CK2 are delayed by half a period when a write operation is switched to a read operation with data being outputted at a selector 62 in an appropriate order accordingly. Traced-back data is then inputted from terminal A and terminal B to the selector 62 and outputted from a terminal X after one of these items of data has been selected at a prescribed timing.
公开/授权文献
- EP0798867A2 Viterbi decoding 公开/授权日:1997-10-01
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