发明公开
- 专利标题: Analog FIFO memory and switching device
- 专利标题(中): Analoge FIFO-Speicher und Schaltvorrichtung
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申请号: EP97108492.6申请日: 1997-05-26
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公开(公告)号: EP0810730A3公开(公告)日: 1998-04-29
- 发明人: Dosho, Shiro , Kurimoto, Hidehiko , Yanagisawa, Naoshi
- 申请人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 申请人地址: 1006, Ohaza Kadoma Kadoma-shi, Osaka 571 JP
- 专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人地址: 1006, Ohaza Kadoma Kadoma-shi, Osaka 571 JP
- 代理机构: Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
- 优先权: JP132965/96 19960528; JP264280/96 19961004
- 主分类号: H03H19/00
- IPC分类号: H03H19/00 ; H04N9/78
摘要:
The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.
公开/授权文献
- EP0810730B1 Analog FIFO memory 公开/授权日:2003-01-15
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