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1.发明公开
公开(公告)号：EP1115198A2
公开(公告)日：2001-07-11
申请号：EP00128707.7
申请日：2000-12-29
CPC分类号： H03D13/004 , H03L7/087 , H03L7/0891 , H03L7/18
摘要： A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.
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公开(公告)号：EP0810730A3
公开(公告)日：1998-04-29
申请号：EP97108492.6
申请日：1997-05-26
CPC分类号： G11C27/04 , G11C27/00 , H03H19/004 , H04N9/78
摘要： The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.
摘要翻译： 本发明提供了一种模拟FIFO存储器，用于以输入顺序输出具有预定时间延迟的输入模拟信号，包括存储器总线电路，该存储器总线电路包括用于存储模拟信号的多个存储单元，以及与所述存储器连接的存储器总线 用于传送模拟信号的单元，其中每个所述存储单元包括用于以电荷形式存储模拟信号的电容装置; 以及用于控制所述电容器件和所述存储器总线之间的连接的开关，当选择一个存储器单元进行读取/写入时，所述选择的存储器单元的所述开关在读取操作和写入操作中处于开启状态，以及 所述存储器总线电路还包括具有与所述存储器总线连接的电容器件的虚拟存储器单元。
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公开(公告)号：EP1132963A1
公开(公告)日：2001-09-12
申请号：EP01104590.3
申请日：2001-03-06
IPC分类号： H01L23/50
CPC分类号： H03K17/005 , H01L24/06 , H01L2224/05554 , H01L2224/49175 , H01L2924/14 , H03K3/03 , H03K17/693 , Y10T307/391 , Y10T307/461 , Y10T307/492 , H01L2924/00
摘要： A semiconductor integrated circuit includes a plurality of units. Each of the units includes a power supply pad, a function circuit, and a power supply control circuit. The plurality of units each have a first state in which the function circuit is in an operating state by the power supply pad being at a prescribed operating potential and a second state in which the function circuit is in a non-operating state by the power supply pad being at a prescribed non-operating potential. The power supply control circuit includes a switching circuit for connecting the power supply pad to the prescribed non-operating potential. The power supply control circuit in each of the plurality of units closes the switching circuit when at least one of the other units is in the first state and opens the switching circuit otherwise.
摘要翻译： 半导体集成电路包括多个单元。 每个单元包括电源焊盘，功能电路和电源控制电路。 多个单元中的每一个都具有第一状态和第二状态，在第一状态中，功能电路处于由电源焊盘处于规定工作电位的工作状态和第二状态中，其中功能电路由电源处于非工作状态 垫处于规定的非操作电位。 电源控制电路包括用于将电源焊盘连接到规定的非工作电位的开关电路。 当其他单元中的至少一个单元处于第一状态时，多个单元中的每个单元中的电源控制电路闭合开关电路，否则断开开关电路。
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公开(公告)号：EP0810730A2
公开(公告)日：1997-12-03
申请号：EP97108492.6
申请日：1997-05-26
CPC分类号： G11C27/04 , G11C27/00 , H03H19/004 , H04N9/78
摘要： The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.
摘要翻译： 本发明提供一种模拟FIFO存储器，通过消除写入操作和读取操作之间的模拟信号中的错误，可以从中准确地读取写入的模拟信号。 在通过存储器总线从存储器单元读取模拟信号的读取操作之前，进行用于将存储器总线设置在预定电位的复位操作，以便去除存储在存储器总线的寄生电容中的电荷。 读取电路的输入端子通过使用输入电路和通过使用输出电路与存储器总线连接的读取电路将写入电路从存储器总线断开而被设置在预定电位。 以这种方式，将存储器总线设置在预定电位，并且存储在寄生电容中的电荷被放电。 此时，每个存储器单元中的开关处于截止状态，因此可以将与模拟信号相对应的电荷保留在存储单元中。
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公开(公告)号：EP0878770B1
公开(公告)日：2008-07-16
申请号：EP98108812.3
申请日：1998-05-14
发明人： Dosho, Shiro , Yanagisawa, Naoshi
CPC分类号： G06J1/00
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7.发明授权
公开(公告)号：EP1115198B1
公开(公告)日：2004-03-03
申请号：EP00128707.7
申请日：2000-12-29
CPC分类号： H03D13/004 , H03L7/087 , H03L7/0891 , H03L7/18
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公开(公告)号：EP0878770A3
公开(公告)日：2002-01-02
申请号：EP98108812.3
申请日：1998-05-14
发明人： Dosho, Shiro , Yanagisawa, Naoshi
CPC分类号： G06J1/00
摘要： An analog FIFO memory device allowing for the suppression of the adverse effects produced by fixed pattern noise, generated inside an analog FIFO memory, on signal components. First and second analog multipliers are respectively provided on the input and output sides of the analog FIFO memory. In synchronism with the inputs/outputs of signals to/from the analog FIFO memory, a non-inverting operation and an inverting operation are alternately and repeatedly performed on the input signals and the output signals. Then, although the signal input/output characteristics of the analog FIFO memory are not changed, the fixed pattern noise generated inside the analog FIFO memory is modulated by the second analog multiplier. As a result, the spectrum of the fixed pattern noise, which originally has a lower frequency, is shifted to have a higher frequency. That is to say, since a signal band can be separated from the fixed pattern noise in terms of frequency, the fixed pattern noise can be eliminated by a low pass filter. Consequently, even when the analog FIFO memory device of the present invention is applied for delaying TV signals, the resulting TV image quality is not deteriorated.
摘要翻译： 一种模拟FIFO存储器件，可以抑制由模拟FIFO存储器内部产生的固定模式噪声对信号分量产生的不利影响。 第一和第二模拟乘法器分别设置在模拟FIFO存储器的输入和输出侧。 与来自/来自模拟FIFO存储器的信号的输入/输出同步，对输入信号和输出信号交替地和重复地执行非反相操作和反相操作。 然后，尽管模拟FIFO存储器的信号输入/输出特性没有改变，但模拟FIFO存储器内产生的固定模式噪声由第二个模拟乘法器调制。 结果，原本具有较低频率的固定模式噪声的频谱被移位以具有较高的频率。 也就是说，由于信号频带在频率方面可以与固定模式噪声分离，固定模式噪声可以通过低通滤波器消除。 因此，即使在应用本发明的模拟FIFO存储装置来延迟电视信号时，所得到的电视图像质量也不会恶化。
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9.发明公开Jitter detector, phase difference detector and jitter detecting method 审中-公开Jitter und Fasendetektor und dessen Detektionsverfahren
公开(公告)号：EP1096263A2
公开(公告)日：2001-05-02
申请号：EP00123243.8
申请日：2000-10-26
IPC分类号： G01R25/00
CPC分类号： G01R25/00
摘要： A jitter detector obtains a phase difference between input signals as a digital value to make jitter between the signals easily detectable. The jitter detector includes comparison pulse generator, periodic signal generator, counter and arithmetic unit. The comparison pulse generator outputs one phase difference comparison pulse after another. Each phase difference comparison pulse has a width representing the phase difference between first and second input signals. The periodic signal generator outputs a periodic signal every time a value obtained by accumulating the widths of the phase difference comparison pulses exceeds a predetermined value. Receiving the periodic signal and a clock signal with a period shorter than that of the periodic signal, the counter counts the number of pulses of the clock signal during one period of the periodic signal and outputs a resultant count. And the arithmetic unit detects and outputs a variation in the count as jitter between the first and second input signals.
摘要翻译： 抖动检测器获得输入信号之间的相位差作为数字值，使得信号之间的抖动容易检测。 抖动检测器包括比较脉冲发生器，周期信号发生器，计数器和运算单元。 比较脉冲发生器输出一个相位差比较脉冲。 每个相位差比较脉冲具有表示第一和第二输入信号之间的相位差的宽度。 每当通过累积相位差比较脉冲的宽度获得的值超过预定值时，周期性信号发生器输出周期信号。 接收到周期信号和周期信号的周期信号的时钟信号，计数器在周期信号的一个周期内对时钟信号的脉冲数进行计数并输出结果计数。 并且算术单元检测并输出计数的变化，作为第一和第二输入信号之间的抖动。
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公开(公告)号：EP1139563B1
公开(公告)日：2004-11-03
申请号：EP01110322.3
申请日：1997-05-26
CPC分类号： G11C27/04 , G11C27/00 , H03H19/004 , H04N9/78
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