发明公开
- 专利标题： PARALLEL ACCESS MICRO-TLB TO SPEED UP ADDRESS TRANSLATION
- 专利标题（中）： 具有并行访问，加速地址转换微型TLB
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申请号： EP96911211申请日： 1996-02-29
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公开(公告)号： EP0813709A1公开(公告)日： 1997-12-29
- 发明人: CHANG CHIH-WEI DAVID , DAWALLU KIOUMARS , BONEY JOEL F , LI MING-YING , CHEN JEN-HONG CHARLES
- 申请人： HAL COMPUTER SYSTEMS INC
- 专利权人： HAL COMPUTER SYSTEMS INC
- 当前专利权人： HAL COMPUTER SYSTEMS INC
- 优先权： US39781095 1995-03-03
- 主分类号： G06F12/08
- IPC分类号： G06F12/08 ; G06F12/10 ; G06F9/26 ; G06F9/34 ; G06F12/00 ; G06F12/04
摘要：
A memory management unit (124) (MMU) includes a translation lookaside buffer (108) capable of simultaneously servicing three requests supplied to the MMU by an instruction cache (102) and two data caches (103, 104), respectively. Also, an arbiter (113) selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority.
公开/授权文献
- EP0813709A4 PARALLEL ACCESS MICRO-TLB TO SPEED UP ADDRESS TRANSLATION 公开/授权日：2001-02-07
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